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+NVIDIA Tegra Video Decoder Engine
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+
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+Required properties:
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+- compatible : Must contain one of the following values:
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+ - "nvidia,tegra20-vde"
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+ - "nvidia,tegra30-vde"
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+ - "nvidia,tegra114-vde"
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+ - "nvidia,tegra124-vde"
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+ - "nvidia,tegra132-vde"
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+- reg : Must contain an entry for each entry in reg-names.
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+- reg-names : Must include the following entries:
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+ - sxe
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+ - bsev
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+ - mbe
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+ - ppe
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+ - mce
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+ - tfe
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+ - ppb
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+ - vdma
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+ - frameid
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+- iram : Must contain phandle to the mmio-sram device node that represents
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+ IRAM region used by VDE.
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+- interrupts : Must contain an entry for each entry in interrupt-names.
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+- interrupt-names : Must include the following entries:
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+ - sync-token
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+ - bsev
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+ - sxe
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+- clocks : Must include the following entries:
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+ - vde
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+- resets : Must include the following entries:
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+ - vde
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+
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+Example:
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+
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+video-codec@6001a000 {
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+ compatible = "nvidia,tegra20-vde";
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+ reg = <0x6001a000 0x1000 /* Syntax Engine */
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+ 0x6001b000 0x1000 /* Video Bitstream Engine */
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+ 0x6001c000 0x100 /* Macroblock Engine */
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+ 0x6001c200 0x100 /* Post-processing Engine */
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+ 0x6001c400 0x100 /* Motion Compensation Engine */
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+ 0x6001c600 0x100 /* Transform Engine */
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+ 0x6001c800 0x100 /* Pixel prediction block */
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+ 0x6001ca00 0x100 /* Video DMA */
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+ 0x6001d800 0x300 /* Video frame controls */>;
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+ reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
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+ "tfe", "ppb", "vdma", "frameid";
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+ iram = <&vde_pool>; /* IRAM region */
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+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
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+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
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+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
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+ interrupt-names = "sync-token", "bsev", "sxe";
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+ clocks = <&tegra_car TEGRA20_CLK_VDE>;
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+ resets = <&tegra_car 61>;
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+};
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