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@@ -243,6 +243,16 @@ static inline void ath10k_ce_error_intr_enable(struct ath10k *ar,
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misc_ie_addr | CE_ERROR_MASK);
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}
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+static inline void ath10k_ce_error_intr_disable(struct ath10k *ar,
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+ u32 ce_ctrl_addr)
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+{
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+ u32 misc_ie_addr = ath10k_pci_read32(ar,
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+ ce_ctrl_addr + MISC_IE_ADDRESS);
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+
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+ ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,
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+ misc_ie_addr & ~CE_ERROR_MASK);
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+}
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+
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static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar,
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u32 ce_ctrl_addr,
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unsigned int mask)
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@@ -794,6 +804,8 @@ void ath10k_ce_disable_interrupts(struct ath10k *ar)
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u32 ctrl_addr = ath10k_ce_base_address(ce_id);
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ath10k_ce_copy_complete_intr_disable(ar, ctrl_addr);
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+ ath10k_ce_error_intr_disable(ar, ctrl_addr);
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+ ath10k_ce_watermark_intr_disable(ar, ctrl_addr);
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}
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ath10k_pci_sleep(ar);
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}
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