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@@ -164,4 +164,35 @@
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* authoritative source for all of these.
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*/
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+/* Intel framebuffer modifiers */
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+
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+/*
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+ * Intel X-tiling layout
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+ *
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+ * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
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+ * in row-major layout. Within the tile bytes are laid out row-major, with
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+ * a platform-dependent stride. On top of that the memory can apply
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+ * platform-depending swizzling of some higher address bits into bit6.
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+ *
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+ * This format is highly platforms specific and not useful for cross-driver
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+ * sharing. It exists since on a given platform it does uniquely identify the
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+ * layout in a simple way for i915-specific userspace.
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+ */
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+#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
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+
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+/*
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+ * Intel Y-tiling layout
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+ *
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+ * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
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+ * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
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+ * chunks column-major, with a platform-dependent height. On top of that the
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+ * memory can apply platform-depending swizzling of some higher address bits
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+ * into bit6.
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+ *
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+ * This format is highly platforms specific and not useful for cross-driver
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+ * sharing. It exists since on a given platform it does uniquely identify the
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+ * layout in a simple way for i915-specific userspace.
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+ */
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+#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
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+
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#endif /* DRM_FOURCC_H */
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