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@@ -533,40 +533,40 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
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tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
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tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
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dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
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- } else {
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- dev_info(dev, "Link: Gen2 disabled\n");
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- }
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-
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- /*
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- * Start Directed Speed Change so the best possible speed both link
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- * partners support can be negotiated.
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- */
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- tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
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- tmp |= PORT_LOGIC_SPEED_CHANGE;
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- dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
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- if (imx6_pcie->variant != IMX7D) {
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/*
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- * On i.MX7, DIRECT_SPEED_CHANGE behaves differently
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- * from i.MX6 family when no link speed transition
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- * occurs and we go Gen1 -> yep, Gen1. The difference
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- * is that, in such case, it will not be cleared by HW
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- * which will cause the following code to report false
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- * failure.
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+ * Start Directed Speed Change so the best possible
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+ * speed both link partners support can be negotiated.
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*/
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+ tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
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+ tmp |= PORT_LOGIC_SPEED_CHANGE;
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+ dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
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+
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+ if (imx6_pcie->variant != IMX7D) {
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+ /*
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+ * On i.MX7, DIRECT_SPEED_CHANGE behaves differently
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+ * from i.MX6 family when no link speed transition
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+ * occurs and we go Gen1 -> yep, Gen1. The difference
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+ * is that, in such case, it will not be cleared by HW
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+ * which will cause the following code to report false
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+ * failure.
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+ */
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+
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+ ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
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+ if (ret) {
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+ dev_err(dev, "Failed to bring link up!\n");
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+ goto err_reset_phy;
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+ }
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+ }
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- ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
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+ /* Make sure link training is finished as well! */
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+ ret = imx6_pcie_wait_for_link(imx6_pcie);
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if (ret) {
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dev_err(dev, "Failed to bring link up!\n");
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goto err_reset_phy;
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}
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- }
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-
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- /* Make sure link training is finished as well! */
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- ret = imx6_pcie_wait_for_link(imx6_pcie);
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- if (ret) {
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- dev_err(dev, "Failed to bring link up!\n");
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- goto err_reset_phy;
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+ } else {
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+ dev_info(dev, "Link: Gen2 disabled\n");
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}
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tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);
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