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@@ -21,6 +21,7 @@
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#define SCU_STANDBY_ENABLE (1 << 5)
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#define SCU_CONFIG 0x04
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#define SCU_CPU_STATUS 0x08
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+#define SCU_CPU_STATUS_MASK GENMASK(1, 0)
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#define SCU_INVALIDATE 0x0c
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#define SCU_FPGA_REVISION 0x10
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@@ -82,7 +83,8 @@ static int scu_set_power_mode_internal(void __iomem *scu_base,
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if (mode > 3 || mode == 1 || cpu > 3)
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return -EINVAL;
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- val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
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+ val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
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+ val &= ~SCU_CPU_STATUS_MASK;
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val |= mode;
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writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);
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@@ -109,3 +111,17 @@ int scu_cpu_power_enable(void __iomem *scu_base, unsigned int cpu)
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{
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return scu_set_power_mode_internal(scu_base, cpu, SCU_PM_NORMAL);
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}
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+
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+int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu)
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+{
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+ unsigned int val;
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+ int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0);
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+
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+ if (cpu > 3)
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+ return -EINVAL;
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+
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+ val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);
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+ val &= SCU_CPU_STATUS_MASK;
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+
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+ return val;
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+}
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