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@@ -1320,6 +1320,7 @@ static void imx_flush_buffer(struct uart_port *port)
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struct imx_port *sport = (struct imx_port *)port;
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struct imx_port *sport = (struct imx_port *)port;
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struct scatterlist *sgl = &sport->tx_sgl[0];
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struct scatterlist *sgl = &sport->tx_sgl[0];
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unsigned long temp;
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unsigned long temp;
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+ int i = 100, ubir, ubmr, ubrc, uts;
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if (!sport->dma_chan_tx)
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if (!sport->dma_chan_tx)
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return;
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return;
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@@ -1334,6 +1335,31 @@ static void imx_flush_buffer(struct uart_port *port)
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writel(temp, sport->port.membase + UCR1);
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writel(temp, sport->port.membase + UCR1);
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sport->dma_is_txing = false;
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sport->dma_is_txing = false;
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}
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}
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+
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+ /*
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+ * According to the Reference Manual description of the UART SRST bit:
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+ * "Reset the transmit and receive state machines,
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+ * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
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+ * and UTS[6-3]". As we don't need to restore the old values from
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+ * USR1, USR2, URXD, UTXD, only save/restore the other four registers
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+ */
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+ ubir = readl(sport->port.membase + UBIR);
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+ ubmr = readl(sport->port.membase + UBMR);
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+ ubrc = readl(sport->port.membase + UBRC);
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+ uts = readl(sport->port.membase + IMX21_UTS);
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+
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+ temp = readl(sport->port.membase + UCR2);
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+ temp &= ~UCR2_SRST;
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+ writel(temp, sport->port.membase + UCR2);
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+
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+ while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
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+ udelay(1);
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+
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+ /* Restore the registers */
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+ writel(ubir, sport->port.membase + UBIR);
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+ writel(ubmr, sport->port.membase + UBMR);
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+ writel(ubrc, sport->port.membase + UBRC);
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+ writel(uts, sport->port.membase + IMX21_UTS);
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}
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}
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static void
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static void
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