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@@ -139,6 +139,11 @@
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#define SND_SOC_TPLG_DAI_FLGBIT_SYMMETRIC_CHANNELS (1 << 1)
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#define SND_SOC_TPLG_DAI_FLGBIT_SYMMETRIC_CHANNELS (1 << 1)
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#define SND_SOC_TPLG_DAI_FLGBIT_SYMMETRIC_SAMPLEBITS (1 << 2)
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#define SND_SOC_TPLG_DAI_FLGBIT_SYMMETRIC_SAMPLEBITS (1 << 2)
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+/* DAI clock gating */
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+#define SND_SOC_TPLG_DAI_CLK_GATE_UNDEFINED 0
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+#define SND_SOC_TPLG_DAI_CLK_GATE_GATED 1
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+#define SND_SOC_TPLG_DAI_CLK_GATE_CONT 2
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+
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/* DAI physical PCM data formats.
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/* DAI physical PCM data formats.
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* Add new formats to the end of the list.
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* Add new formats to the end of the list.
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*/
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*/
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@@ -324,7 +329,7 @@ struct snd_soc_tplg_hw_config {
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__le32 size; /* in bytes of this structure */
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__le32 size; /* in bytes of this structure */
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__le32 id; /* unique ID - - used to match */
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__le32 id; /* unique ID - - used to match */
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__le32 fmt; /* SND_SOC_DAI_FORMAT_ format value */
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__le32 fmt; /* SND_SOC_DAI_FORMAT_ format value */
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- __u8 clock_gated; /* 1 if clock can be gated to save power */
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+ __u8 clock_gated; /* SND_SOC_TPLG_DAI_CLK_GATE_ value */
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__u8 invert_bclk; /* 1 for inverted BCLK, 0 for normal */
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__u8 invert_bclk; /* 1 for inverted BCLK, 0 for normal */
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__u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */
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__u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */
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__u8 bclk_master; /* SND_SOC_TPLG_BCLK_ value */
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__u8 bclk_master; /* SND_SOC_TPLG_BCLK_ value */
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