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@@ -0,0 +1,807 @@
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+/* SPDX-License-Identifier: MIT */
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+/*
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+ * Copyright (C) 2017 Google, Inc.
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+ *
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+ * Authors:
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+ * Sean Paul <seanpaul@chromium.org>
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+ */
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+
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+#include <drm/drmP.h>
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+#include <drm/drm_hdcp.h>
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+#include <linux/i2c.h>
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+#include <linux/random.h>
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+
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+#include "intel_drv.h"
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+#include "i915_reg.h"
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+
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+#define KEY_LOAD_TRIES 5
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+
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+static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
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+ const struct intel_hdcp_shim *shim)
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+{
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+ int ret, read_ret;
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+ bool ksv_ready;
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+
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+ /* Poll for ksv list ready (spec says max time allowed is 5s) */
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+ ret = __wait_for(read_ret = shim->read_ksv_ready(intel_dig_port,
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+ &ksv_ready),
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+ read_ret || ksv_ready, 5 * 1000 * 1000, 1000,
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+ 100 * 1000);
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+ if (ret)
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+ return ret;
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+ if (read_ret)
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+ return read_ret;
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+ if (!ksv_ready)
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+ return -ETIMEDOUT;
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+
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+ return 0;
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+}
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+
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+static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv)
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+{
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+ I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);
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+ I915_WRITE(HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS |
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+ HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE);
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+}
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+
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+static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
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+{
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+ int ret;
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+ u32 val;
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+
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+ val = I915_READ(HDCP_KEY_STATUS);
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+ if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS))
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+ return 0;
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+
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+ /*
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+ * On HSW and BDW HW loads the HDCP1.4 Key when Display comes
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+ * out of reset. So if Key is not already loaded, its an error state.
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+ */
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+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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+ if (!(I915_READ(HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE))
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+ return -ENXIO;
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+
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+ /*
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+ * Initiate loading the HDCP key from fuses.
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+ *
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+ * BXT+ platforms, HDCP key needs to be loaded by SW. Only SKL and KBL
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+ * differ in the key load trigger process from other platforms.
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+ */
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+ if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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+ mutex_lock(&dev_priv->pcu_lock);
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+ ret = sandybridge_pcode_write(dev_priv,
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+ SKL_PCODE_LOAD_HDCP_KEYS, 1);
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+ mutex_unlock(&dev_priv->pcu_lock);
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+ if (ret) {
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+ DRM_ERROR("Failed to initiate HDCP key load (%d)\n",
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+ ret);
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+ return ret;
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+ }
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+ } else {
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+ I915_WRITE(HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER);
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+ }
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+
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+ /* Wait for the keys to load (500us) */
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+ ret = __intel_wait_for_register(dev_priv, HDCP_KEY_STATUS,
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+ HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE,
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+ 10, 1, &val);
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+ if (ret)
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+ return ret;
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+ else if (!(val & HDCP_KEY_LOAD_STATUS))
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+ return -ENXIO;
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+
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+ /* Send Aksv over to PCH display for use in authentication */
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+ I915_WRITE(HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER);
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+
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+ return 0;
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+}
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+
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+/* Returns updated SHA-1 index */
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+static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text)
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+{
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+ I915_WRITE(HDCP_SHA_TEXT, sha_text);
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+ if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
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+ HDCP_SHA1_READY, HDCP_SHA1_READY, 1)) {
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+ DRM_ERROR("Timed out waiting for SHA1 ready\n");
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+ return -ETIMEDOUT;
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+ }
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+ return 0;
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+}
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+
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+static
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+u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port)
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+{
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+ enum port port = intel_dig_port->base.port;
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+ switch (port) {
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+ case PORT_A:
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+ return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
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+ case PORT_B:
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+ return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0;
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+ case PORT_C:
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+ return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0;
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+ case PORT_D:
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+ return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0;
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+ case PORT_E:
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+ return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
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+ default:
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+ break;
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+ }
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+ DRM_ERROR("Unknown port %d\n", port);
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+ return -EINVAL;
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+}
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+
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+static
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+bool intel_hdcp_is_ksv_valid(u8 *ksv)
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+{
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+ int i, ones = 0;
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+ /* KSV has 20 1's and 20 0's */
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+ for (i = 0; i < DRM_HDCP_KSV_LEN; i++)
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+ ones += hweight8(ksv[i]);
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+ if (ones != 20)
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+ return false;
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+ return true;
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+}
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+
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+/* Implements Part 2 of the HDCP authorization procedure */
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+static
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+int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
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+ const struct intel_hdcp_shim *shim)
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+{
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+ struct drm_i915_private *dev_priv;
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+ u32 vprime, sha_text, sha_leftovers, rep_ctl;
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+ u8 bstatus[2], num_downstream, *ksv_fifo;
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+ int ret, i, j, sha_idx;
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+
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+ dev_priv = intel_dig_port->base.base.dev->dev_private;
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+
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+ ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
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+ if (ret) {
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+ DRM_ERROR("KSV list failed to become ready (%d)\n", ret);
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+ return ret;
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+ }
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+
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+ ret = shim->read_bstatus(intel_dig_port, bstatus);
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+ if (ret)
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+ return ret;
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+
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+ if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
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+ DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
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+ DRM_ERROR("Max Topology Limit Exceeded\n");
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+ return -EPERM;
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+ }
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+
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+ /*
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+ * When repeater reports 0 device count, HDCP1.4 spec allows disabling
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+ * the HDCP encryption. That implies that repeater can't have its own
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+ * display. As there is no consumption of encrypted content in the
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+ * repeater with 0 downstream devices, we are failing the
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+ * authentication.
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+ */
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+ num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
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+ if (num_downstream == 0)
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+ return -EINVAL;
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+
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+ ksv_fifo = kzalloc(num_downstream * DRM_HDCP_KSV_LEN, GFP_KERNEL);
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+ if (!ksv_fifo)
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+ return -ENOMEM;
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+
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+ ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
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+ if (ret)
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+ return ret;
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+
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+ /* Process V' values from the receiver */
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+ for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) {
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+ ret = shim->read_v_prime_part(intel_dig_port, i, &vprime);
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+ if (ret)
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+ return ret;
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+ I915_WRITE(HDCP_SHA_V_PRIME(i), vprime);
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+ }
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+
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+ /*
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+ * We need to write the concatenation of all device KSVs, BINFO (DP) ||
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+ * BSTATUS (HDMI), and M0 (which is added via HDCP_REP_CTL). This byte
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+ * stream is written via the HDCP_SHA_TEXT register in 32-bit
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+ * increments. Every 64 bytes, we need to write HDCP_REP_CTL again. This
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+ * index will keep track of our progress through the 64 bytes as well as
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+ * helping us work the 40-bit KSVs through our 32-bit register.
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+ *
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+ * NOTE: data passed via HDCP_SHA_TEXT should be big-endian
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+ */
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+ sha_idx = 0;
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+ sha_text = 0;
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+ sha_leftovers = 0;
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+ rep_ctl = intel_hdcp_get_repeater_ctl(intel_dig_port);
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+ I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
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+ for (i = 0; i < num_downstream; i++) {
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+ unsigned int sha_empty;
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+ u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN];
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+
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+ /* Fill up the empty slots in sha_text and write it out */
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+ sha_empty = sizeof(sha_text) - sha_leftovers;
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+ for (j = 0; j < sha_empty; j++)
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+ sha_text |= ksv[j] << ((sizeof(sha_text) - j - 1) * 8);
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+
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+ ret = intel_write_sha_text(dev_priv, sha_text);
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+ if (ret < 0)
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+ return ret;
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+
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+ /* Programming guide writes this every 64 bytes */
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+ sha_idx += sizeof(sha_text);
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+ if (!(sha_idx % 64))
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+ I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
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+
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+ /* Store the leftover bytes from the ksv in sha_text */
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+ sha_leftovers = DRM_HDCP_KSV_LEN - sha_empty;
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+ sha_text = 0;
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+ for (j = 0; j < sha_leftovers; j++)
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+ sha_text |= ksv[sha_empty + j] <<
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+ ((sizeof(sha_text) - j - 1) * 8);
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+
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+ /*
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+ * If we still have room in sha_text for more data, continue.
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+ * Otherwise, write it out immediately.
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+ */
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+ if (sizeof(sha_text) > sha_leftovers)
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+ continue;
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+
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+ ret = intel_write_sha_text(dev_priv, sha_text);
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+ if (ret < 0)
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+ return ret;
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+ sha_leftovers = 0;
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+ sha_text = 0;
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+ sha_idx += sizeof(sha_text);
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+ }
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+
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+ /*
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+ * We need to write BINFO/BSTATUS, and M0 now. Depending on how many
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+ * bytes are leftover from the last ksv, we might be able to fit them
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+ * all in sha_text (first 2 cases), or we might need to split them up
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+ * into 2 writes (last 2 cases).
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+ */
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+ if (sha_leftovers == 0) {
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+ /* Write 16 bits of text, 16 bits of M0 */
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+ I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_16);
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+ ret = intel_write_sha_text(dev_priv,
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+ bstatus[0] << 8 | bstatus[1]);
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+ if (ret < 0)
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+ return ret;
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+ sha_idx += sizeof(sha_text);
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+
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+ /* Write 32 bits of M0 */
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+ I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0);
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+ ret = intel_write_sha_text(dev_priv, 0);
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+ if (ret < 0)
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+ return ret;
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+ sha_idx += sizeof(sha_text);
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+
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+ /* Write 16 bits of M0 */
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+ I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_16);
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+ ret = intel_write_sha_text(dev_priv, 0);
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+ if (ret < 0)
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+ return ret;
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+ sha_idx += sizeof(sha_text);
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+
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+ } else if (sha_leftovers == 1) {
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+ /* Write 24 bits of text, 8 bits of M0 */
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+ I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_24);
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+ sha_text |= bstatus[0] << 16 | bstatus[1] << 8;
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+ /* Only 24-bits of data, must be in the LSB */
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+ sha_text = (sha_text & 0xffffff00) >> 8;
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+ ret = intel_write_sha_text(dev_priv, sha_text);
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+ if (ret < 0)
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+ return ret;
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+ sha_idx += sizeof(sha_text);
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+
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+ /* Write 32 bits of M0 */
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+ I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0);
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+ ret = intel_write_sha_text(dev_priv, 0);
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+ if (ret < 0)
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+ return ret;
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+ sha_idx += sizeof(sha_text);
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+
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+ /* Write 24 bits of M0 */
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+ I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_8);
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+ ret = intel_write_sha_text(dev_priv, 0);
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+ if (ret < 0)
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+ return ret;
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+ sha_idx += sizeof(sha_text);
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+
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+ } else if (sha_leftovers == 2) {
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+ /* Write 32 bits of text */
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+ I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
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+ sha_text |= bstatus[0] << 24 | bstatus[1] << 16;
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+ ret = intel_write_sha_text(dev_priv, sha_text);
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+ if (ret < 0)
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+ return ret;
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+ sha_idx += sizeof(sha_text);
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+
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+ /* Write 64 bits of M0 */
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+ I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0);
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+ for (i = 0; i < 2; i++) {
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+ ret = intel_write_sha_text(dev_priv, 0);
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+ if (ret < 0)
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+ return ret;
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+ sha_idx += sizeof(sha_text);
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+ }
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+ } else if (sha_leftovers == 3) {
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+ /* Write 32 bits of text */
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+ I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
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+ sha_text |= bstatus[0] << 24;
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+ ret = intel_write_sha_text(dev_priv, sha_text);
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+ if (ret < 0)
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+ return ret;
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+ sha_idx += sizeof(sha_text);
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+
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+ /* Write 8 bits of text, 24 bits of M0 */
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+ I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_8);
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+ ret = intel_write_sha_text(dev_priv, bstatus[1]);
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+ if (ret < 0)
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+ return ret;
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+ sha_idx += sizeof(sha_text);
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+
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+ /* Write 32 bits of M0 */
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+ I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0);
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+ ret = intel_write_sha_text(dev_priv, 0);
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+ if (ret < 0)
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+ return ret;
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+ sha_idx += sizeof(sha_text);
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+
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+ /* Write 8 bits of M0 */
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+ I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_24);
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+ ret = intel_write_sha_text(dev_priv, 0);
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+ if (ret < 0)
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+ return ret;
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+ sha_idx += sizeof(sha_text);
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+ } else {
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+ DRM_ERROR("Invalid number of leftovers %d\n", sha_leftovers);
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+ return -EINVAL;
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+ }
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+
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+ I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
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+ /* Fill up to 64-4 bytes with zeros (leave the last write for length) */
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+ while ((sha_idx % 64) < (64 - sizeof(sha_text))) {
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+ ret = intel_write_sha_text(dev_priv, 0);
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+ if (ret < 0)
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+ return ret;
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+ sha_idx += sizeof(sha_text);
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+ }
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+
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+ /*
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+ * Last write gets the length of the concatenation in bits. That is:
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+ * - 5 bytes per device
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+ * - 10 bytes for BINFO/BSTATUS(2), M0(8)
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+ */
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|
|
+ sha_text = (num_downstream * 5 + 10) * 8;
|
|
|
+ ret = intel_write_sha_text(dev_priv, sha_text);
|
|
|
+ if (ret < 0)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ /* Tell the HW we're done with the hash and wait for it to ACK */
|
|
|
+ I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_COMPLETE_HASH);
|
|
|
+ if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
|
|
|
+ HDCP_SHA1_COMPLETE,
|
|
|
+ HDCP_SHA1_COMPLETE, 1)) {
|
|
|
+ DRM_ERROR("Timed out waiting for SHA1 complete\n");
|
|
|
+ return -ETIMEDOUT;
|
|
|
+ }
|
|
|
+ if (!(I915_READ(HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) {
|
|
|
+ DRM_ERROR("SHA-1 mismatch, HDCP failed\n");
|
|
|
+ return -ENXIO;
|
|
|
+ }
|
|
|
+
|
|
|
+ DRM_DEBUG_KMS("HDCP is enabled (%d downstream devices)\n",
|
|
|
+ num_downstream);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+/* Implements Part 1 of the HDCP authorization procedure */
|
|
|
+static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
|
|
|
+ const struct intel_hdcp_shim *shim)
|
|
|
+{
|
|
|
+ struct drm_i915_private *dev_priv;
|
|
|
+ enum port port;
|
|
|
+ unsigned long r0_prime_gen_start;
|
|
|
+ int ret, i, tries = 2;
|
|
|
+ union {
|
|
|
+ u32 reg[2];
|
|
|
+ u8 shim[DRM_HDCP_AN_LEN];
|
|
|
+ } an;
|
|
|
+ union {
|
|
|
+ u32 reg[2];
|
|
|
+ u8 shim[DRM_HDCP_KSV_LEN];
|
|
|
+ } bksv;
|
|
|
+ union {
|
|
|
+ u32 reg;
|
|
|
+ u8 shim[DRM_HDCP_RI_LEN];
|
|
|
+ } ri;
|
|
|
+ bool repeater_present, hdcp_capable;
|
|
|
+
|
|
|
+ dev_priv = intel_dig_port->base.base.dev->dev_private;
|
|
|
+
|
|
|
+ port = intel_dig_port->base.port;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Detects whether the display is HDCP capable. Although we check for
|
|
|
+ * valid Bksv below, the HDCP over DP spec requires that we check
|
|
|
+ * whether the display supports HDCP before we write An. For HDMI
|
|
|
+ * displays, this is not necessary.
|
|
|
+ */
|
|
|
+ if (shim->hdcp_capable) {
|
|
|
+ ret = shim->hdcp_capable(intel_dig_port, &hdcp_capable);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ if (!hdcp_capable) {
|
|
|
+ DRM_ERROR("Panel is not HDCP capable\n");
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Initialize An with 2 random values and acquire it */
|
|
|
+ for (i = 0; i < 2; i++)
|
|
|
+ I915_WRITE(PORT_HDCP_ANINIT(port), get_random_u32());
|
|
|
+ I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_CAPTURE_AN);
|
|
|
+
|
|
|
+ /* Wait for An to be acquired */
|
|
|
+ if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port),
|
|
|
+ HDCP_STATUS_AN_READY,
|
|
|
+ HDCP_STATUS_AN_READY, 1)) {
|
|
|
+ DRM_ERROR("Timed out waiting for An\n");
|
|
|
+ return -ETIMEDOUT;
|
|
|
+ }
|
|
|
+
|
|
|
+ an.reg[0] = I915_READ(PORT_HDCP_ANLO(port));
|
|
|
+ an.reg[1] = I915_READ(PORT_HDCP_ANHI(port));
|
|
|
+ ret = shim->write_an_aksv(intel_dig_port, an.shim);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ r0_prime_gen_start = jiffies;
|
|
|
+
|
|
|
+ memset(&bksv, 0, sizeof(bksv));
|
|
|
+
|
|
|
+ /* HDCP spec states that we must retry the bksv if it is invalid */
|
|
|
+ for (i = 0; i < tries; i++) {
|
|
|
+ ret = shim->read_bksv(intel_dig_port, bksv.shim);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ if (intel_hdcp_is_ksv_valid(bksv.shim))
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ if (i == tries) {
|
|
|
+ DRM_ERROR("HDCP failed, Bksv is invalid\n");
|
|
|
+ return -ENODEV;
|
|
|
+ }
|
|
|
+
|
|
|
+ I915_WRITE(PORT_HDCP_BKSVLO(port), bksv.reg[0]);
|
|
|
+ I915_WRITE(PORT_HDCP_BKSVHI(port), bksv.reg[1]);
|
|
|
+
|
|
|
+ ret = shim->repeater_present(intel_dig_port, &repeater_present);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ if (repeater_present)
|
|
|
+ I915_WRITE(HDCP_REP_CTL,
|
|
|
+ intel_hdcp_get_repeater_ctl(intel_dig_port));
|
|
|
+
|
|
|
+ ret = shim->toggle_signalling(intel_dig_port, true);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_AUTH_AND_ENC);
|
|
|
+
|
|
|
+ /* Wait for R0 ready */
|
|
|
+ if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
|
|
|
+ (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) {
|
|
|
+ DRM_ERROR("Timed out waiting for R0 ready\n");
|
|
|
+ return -ETIMEDOUT;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Wait for R0' to become available. The spec says 100ms from Aksv, but
|
|
|
+ * some monitors can take longer than this. We'll set the timeout at
|
|
|
+ * 300ms just to be sure.
|
|
|
+ *
|
|
|
+ * On DP, there's an R0_READY bit available but no such bit
|
|
|
+ * exists on HDMI. Since the upper-bound is the same, we'll just do
|
|
|
+ * the stupid thing instead of polling on one and not the other.
|
|
|
+ */
|
|
|
+ wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300);
|
|
|
+
|
|
|
+ ri.reg = 0;
|
|
|
+ ret = shim->read_ri_prime(intel_dig_port, ri.shim);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
|
|
|
+
|
|
|
+ /* Wait for Ri prime match */
|
|
|
+ if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
|
|
|
+ (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
|
|
|
+ DRM_ERROR("Timed out waiting for Ri prime match (%x)\n",
|
|
|
+ I915_READ(PORT_HDCP_STATUS(port)));
|
|
|
+ return -ETIMEDOUT;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Wait for encryption confirmation */
|
|
|
+ if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port),
|
|
|
+ HDCP_STATUS_ENC, HDCP_STATUS_ENC, 20)) {
|
|
|
+ DRM_ERROR("Timed out waiting for encryption\n");
|
|
|
+ return -ETIMEDOUT;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * XXX: If we have MST-connected devices, we need to enable encryption
|
|
|
+ * on those as well.
|
|
|
+ */
|
|
|
+
|
|
|
+ if (repeater_present)
|
|
|
+ return intel_hdcp_auth_downstream(intel_dig_port, shim);
|
|
|
+
|
|
|
+ DRM_DEBUG_KMS("HDCP is enabled (no repeater present)\n");
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static
|
|
|
+struct intel_digital_port *conn_to_dig_port(struct intel_connector *connector)
|
|
|
+{
|
|
|
+ return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
|
|
|
+}
|
|
|
+
|
|
|
+static int _intel_hdcp_disable(struct intel_connector *connector)
|
|
|
+{
|
|
|
+ struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
|
|
|
+ struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
|
|
|
+ enum port port = intel_dig_port->base.port;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ DRM_DEBUG_KMS("[%s:%d] HDCP is being disabled...\n",
|
|
|
+ connector->base.name, connector->base.base.id);
|
|
|
+
|
|
|
+ I915_WRITE(PORT_HDCP_CONF(port), 0);
|
|
|
+ if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port), ~0, 0,
|
|
|
+ 20)) {
|
|
|
+ DRM_ERROR("Failed to disable HDCP, timeout clearing status\n");
|
|
|
+ return -ETIMEDOUT;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = connector->hdcp_shim->toggle_signalling(intel_dig_port, false);
|
|
|
+ if (ret) {
|
|
|
+ DRM_ERROR("Failed to disable HDCP signalling\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ DRM_DEBUG_KMS("HDCP is disabled\n");
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int _intel_hdcp_enable(struct intel_connector *connector)
|
|
|
+{
|
|
|
+ struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
|
|
|
+ int i, ret, tries = 3;
|
|
|
+
|
|
|
+ DRM_DEBUG_KMS("[%s:%d] HDCP is being enabled...\n",
|
|
|
+ connector->base.name, connector->base.base.id);
|
|
|
+
|
|
|
+ if (!(I915_READ(SKL_FUSE_STATUS) & SKL_FUSE_PG_DIST_STATUS(1))) {
|
|
|
+ DRM_ERROR("PG1 is disabled, cannot load keys\n");
|
|
|
+ return -ENXIO;
|
|
|
+ }
|
|
|
+
|
|
|
+ for (i = 0; i < KEY_LOAD_TRIES; i++) {
|
|
|
+ ret = intel_hdcp_load_keys(dev_priv);
|
|
|
+ if (!ret)
|
|
|
+ break;
|
|
|
+ intel_hdcp_clear_keys(dev_priv);
|
|
|
+ }
|
|
|
+ if (ret) {
|
|
|
+ DRM_ERROR("Could not load HDCP keys, (%d)\n", ret);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Incase of authentication failures, HDCP spec expects reauth. */
|
|
|
+ for (i = 0; i < tries; i++) {
|
|
|
+ ret = intel_hdcp_auth(conn_to_dig_port(connector),
|
|
|
+ connector->hdcp_shim);
|
|
|
+ if (!ret)
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ DRM_DEBUG_KMS("HDCP Auth failure (%d)\n", ret);
|
|
|
+
|
|
|
+ /* Ensuring HDCP encryption and signalling are stopped. */
|
|
|
+ _intel_hdcp_disable(connector);
|
|
|
+ }
|
|
|
+
|
|
|
+ DRM_ERROR("HDCP authentication failed (%d tries/%d)\n", tries, ret);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static void intel_hdcp_check_work(struct work_struct *work)
|
|
|
+{
|
|
|
+ struct intel_connector *connector = container_of(to_delayed_work(work),
|
|
|
+ struct intel_connector,
|
|
|
+ hdcp_check_work);
|
|
|
+ if (!intel_hdcp_check_link(connector))
|
|
|
+ schedule_delayed_work(&connector->hdcp_check_work,
|
|
|
+ DRM_HDCP_CHECK_PERIOD_MS);
|
|
|
+}
|
|
|
+
|
|
|
+static void intel_hdcp_prop_work(struct work_struct *work)
|
|
|
+{
|
|
|
+ struct intel_connector *connector = container_of(work,
|
|
|
+ struct intel_connector,
|
|
|
+ hdcp_prop_work);
|
|
|
+ struct drm_device *dev = connector->base.dev;
|
|
|
+ struct drm_connector_state *state;
|
|
|
+
|
|
|
+ drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
|
|
|
+ mutex_lock(&connector->hdcp_mutex);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * This worker is only used to flip between ENABLED/DESIRED. Either of
|
|
|
+ * those to UNDESIRED is handled by core. If hdcp_value == UNDESIRED,
|
|
|
+ * we're running just after hdcp has been disabled, so just exit
|
|
|
+ */
|
|
|
+ if (connector->hdcp_value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
|
|
|
+ state = connector->base.state;
|
|
|
+ state->content_protection = connector->hdcp_value;
|
|
|
+ }
|
|
|
+
|
|
|
+ mutex_unlock(&connector->hdcp_mutex);
|
|
|
+ drm_modeset_unlock(&dev->mode_config.connection_mutex);
|
|
|
+}
|
|
|
+
|
|
|
+bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
|
|
|
+{
|
|
|
+ /* PORT E doesn't have HDCP, and PORT F is disabled */
|
|
|
+ return ((INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
|
|
|
+ !IS_CHERRYVIEW(dev_priv) && port < PORT_E);
|
|
|
+}
|
|
|
+
|
|
|
+int intel_hdcp_init(struct intel_connector *connector,
|
|
|
+ const struct intel_hdcp_shim *hdcp_shim)
|
|
|
+{
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ ret = drm_connector_attach_content_protection_property(
|
|
|
+ &connector->base);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ connector->hdcp_shim = hdcp_shim;
|
|
|
+ mutex_init(&connector->hdcp_mutex);
|
|
|
+ INIT_DELAYED_WORK(&connector->hdcp_check_work, intel_hdcp_check_work);
|
|
|
+ INIT_WORK(&connector->hdcp_prop_work, intel_hdcp_prop_work);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+int intel_hdcp_enable(struct intel_connector *connector)
|
|
|
+{
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ if (!connector->hdcp_shim)
|
|
|
+ return -ENOENT;
|
|
|
+
|
|
|
+ mutex_lock(&connector->hdcp_mutex);
|
|
|
+
|
|
|
+ ret = _intel_hdcp_enable(connector);
|
|
|
+ if (ret)
|
|
|
+ goto out;
|
|
|
+
|
|
|
+ connector->hdcp_value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
|
|
|
+ schedule_work(&connector->hdcp_prop_work);
|
|
|
+ schedule_delayed_work(&connector->hdcp_check_work,
|
|
|
+ DRM_HDCP_CHECK_PERIOD_MS);
|
|
|
+out:
|
|
|
+ mutex_unlock(&connector->hdcp_mutex);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+int intel_hdcp_disable(struct intel_connector *connector)
|
|
|
+{
|
|
|
+ int ret = 0;
|
|
|
+
|
|
|
+ if (!connector->hdcp_shim)
|
|
|
+ return -ENOENT;
|
|
|
+
|
|
|
+ mutex_lock(&connector->hdcp_mutex);
|
|
|
+
|
|
|
+ if (connector->hdcp_value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
|
|
|
+ connector->hdcp_value = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
|
|
|
+ ret = _intel_hdcp_disable(connector);
|
|
|
+ }
|
|
|
+
|
|
|
+ mutex_unlock(&connector->hdcp_mutex);
|
|
|
+ cancel_delayed_work_sync(&connector->hdcp_check_work);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+void intel_hdcp_atomic_check(struct drm_connector *connector,
|
|
|
+ struct drm_connector_state *old_state,
|
|
|
+ struct drm_connector_state *new_state)
|
|
|
+{
|
|
|
+ uint64_t old_cp = old_state->content_protection;
|
|
|
+ uint64_t new_cp = new_state->content_protection;
|
|
|
+ struct drm_crtc_state *crtc_state;
|
|
|
+
|
|
|
+ if (!new_state->crtc) {
|
|
|
+ /*
|
|
|
+ * If the connector is being disabled with CP enabled, mark it
|
|
|
+ * desired so it's re-enabled when the connector is brought back
|
|
|
+ */
|
|
|
+ if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)
|
|
|
+ new_state->content_protection =
|
|
|
+ DRM_MODE_CONTENT_PROTECTION_DESIRED;
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Nothing to do if the state didn't change, or HDCP was activated since
|
|
|
+ * the last commit
|
|
|
+ */
|
|
|
+ if (old_cp == new_cp ||
|
|
|
+ (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
|
|
|
+ new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED))
|
|
|
+ return;
|
|
|
+
|
|
|
+ crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
|
|
|
+ new_state->crtc);
|
|
|
+ crtc_state->mode_changed = true;
|
|
|
+}
|
|
|
+
|
|
|
+/* Implements Part 3 of the HDCP authorization procedure */
|
|
|
+int intel_hdcp_check_link(struct intel_connector *connector)
|
|
|
+{
|
|
|
+ struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
|
|
|
+ struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
|
|
|
+ enum port port = intel_dig_port->base.port;
|
|
|
+ int ret = 0;
|
|
|
+
|
|
|
+ if (!connector->hdcp_shim)
|
|
|
+ return -ENOENT;
|
|
|
+
|
|
|
+ mutex_lock(&connector->hdcp_mutex);
|
|
|
+
|
|
|
+ if (connector->hdcp_value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
|
|
|
+ goto out;
|
|
|
+
|
|
|
+ if (!(I915_READ(PORT_HDCP_STATUS(port)) & HDCP_STATUS_ENC)) {
|
|
|
+ DRM_ERROR("%s:%d HDCP check failed: link is not encrypted,%x\n",
|
|
|
+ connector->base.name, connector->base.base.id,
|
|
|
+ I915_READ(PORT_HDCP_STATUS(port)));
|
|
|
+ ret = -ENXIO;
|
|
|
+ connector->hdcp_value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
|
|
|
+ schedule_work(&connector->hdcp_prop_work);
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (connector->hdcp_shim->check_link(intel_dig_port)) {
|
|
|
+ if (connector->hdcp_value !=
|
|
|
+ DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
|
|
|
+ connector->hdcp_value =
|
|
|
+ DRM_MODE_CONTENT_PROTECTION_ENABLED;
|
|
|
+ schedule_work(&connector->hdcp_prop_work);
|
|
|
+ }
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+
|
|
|
+ DRM_DEBUG_KMS("[%s:%d] HDCP link failed, retrying authentication\n",
|
|
|
+ connector->base.name, connector->base.base.id);
|
|
|
+
|
|
|
+ ret = _intel_hdcp_disable(connector);
|
|
|
+ if (ret) {
|
|
|
+ DRM_ERROR("Failed to disable hdcp (%d)\n", ret);
|
|
|
+ connector->hdcp_value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
|
|
|
+ schedule_work(&connector->hdcp_prop_work);
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = _intel_hdcp_enable(connector);
|
|
|
+ if (ret) {
|
|
|
+ DRM_ERROR("Failed to enable hdcp (%d)\n", ret);
|
|
|
+ connector->hdcp_value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
|
|
|
+ schedule_work(&connector->hdcp_prop_work);
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+
|
|
|
+out:
|
|
|
+ mutex_unlock(&connector->hdcp_mutex);
|
|
|
+ return ret;
|
|
|
+}
|
Dave Airlie