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@@ -984,25 +984,12 @@ static int gic_irq_domain_translate(struct irq_domain *d,
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return -EINVAL;
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return -EINVAL;
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}
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}
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-#ifdef CONFIG_SMP
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-static int gic_secondary_init(struct notifier_block *nfb, unsigned long action,
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- void *hcpu)
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+static int gic_starting_cpu(unsigned int cpu)
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{
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{
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- if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
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- gic_cpu_init(&gic_data[0]);
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- return NOTIFY_OK;
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+ gic_cpu_init(&gic_data[0]);
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+ return 0;
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}
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}
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-/*
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- * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
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- * priority because the GIC needs to be up before the ARM generic timers.
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- */
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-static struct notifier_block gic_cpu_notifier = {
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- .notifier_call = gic_secondary_init,
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- .priority = 100,
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-};
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-#endif
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-
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static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
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static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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unsigned int nr_irqs, void *arg)
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{
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{
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@@ -1148,8 +1135,10 @@ static int __init __gic_init_bases(struct gic_chip_data *gic, int irq_start,
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gic_cpu_map[i] = 0xff;
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gic_cpu_map[i] = 0xff;
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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set_smp_cross_call(gic_raise_softirq);
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set_smp_cross_call(gic_raise_softirq);
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- register_cpu_notifier(&gic_cpu_notifier);
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#endif
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#endif
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+ cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
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+ "AP_IRQ_GIC_STARTING",
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+ gic_starting_cpu, NULL);
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set_handle_irq(gic_handle_irq);
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set_handle_irq(gic_handle_irq);
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if (static_key_true(&supports_deactivate))
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if (static_key_true(&supports_deactivate))
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pr_info("GIC: Using split EOI/Deactivate mode\n");
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pr_info("GIC: Using split EOI/Deactivate mode\n");
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