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@@ -1189,6 +1189,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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struct amdgpu_encoder *aencoder = NULL;
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struct amdgpu_mode_info *mode_info = &adev->mode_info;
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uint32_t link_cnt;
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+ unsigned long possible_crtcs;
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link_cnt = dm->dc->caps.max_links;
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if (amdgpu_dm_mode_config_init(dm->adev)) {
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@@ -1204,7 +1205,18 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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goto fail_free_planes;
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}
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mode_info->planes[i]->base.type = mode_info->plane_type[i];
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- if (amdgpu_dm_plane_init(dm, mode_info->planes[i], 0xff)) {
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+
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+ /*
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+ * HACK: IGT tests expect that each plane can only have one
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+ * one possible CRTC. For now, set one CRTC for each
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+ * plane that is not an underlay, but still allow multiple
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+ * CRTCs for underlay planes.
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+ */
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+ possible_crtcs = 1 << i;
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+ if (i >= dm->dc->caps.max_streams)
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+ possible_crtcs = 0xff;
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+
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+ if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) {
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DRM_ERROR("KMS: Failed to initialize plane\n");
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goto fail_free_planes;
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}
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