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@@ -1119,11 +1119,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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value = ctx->fcr31;
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value = (value & ~FPU_CSR_RM) |
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mips_rm[modeindex(value)];
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-#ifdef CSRTRACE
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- printk("%p gpr[%d]<-csr=%08x\n",
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- (void *) (xcp->cp0_epc),
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- MIPSInst_RT(ir), value);
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-#endif
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+ pr_debug("%p gpr[%d]<-csr=%08x\n",
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+ (void *) (xcp->cp0_epc),
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+ MIPSInst_RT(ir), value);
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}
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else if (MIPSInst_RD(ir) == FPCREG_RID)
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value = 0;
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@@ -1146,11 +1144,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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/* we only have one writable control reg
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*/
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if (MIPSInst_RD(ir) == FPCREG_CSR) {
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-#ifdef CSRTRACE
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- printk("%p gpr[%d]->csr=%08x\n",
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- (void *) (xcp->cp0_epc),
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- MIPSInst_RT(ir), value);
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-#endif
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+ pr_debug("%p gpr[%d]->csr=%08x\n",
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+ (void *) (xcp->cp0_epc),
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+ MIPSInst_RT(ir), value);
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/*
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* Don't write reserved bits,
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