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@@ -937,6 +937,10 @@ void i40e_reset_vf(struct i40e_vf *vf, bool flr)
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wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id), reg);
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wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id), reg);
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i40e_flush(hw);
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i40e_flush(hw);
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}
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}
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+ /* clear the VFLR bit in GLGEN_VFLRSTAT */
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+ reg_idx = (hw->func_caps.vf_base_id + vf->vf_id) / 32;
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+ bit_idx = (hw->func_caps.vf_base_id + vf->vf_id) % 32;
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+ wr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));
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if (i40e_quiesce_vf_pci(vf))
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if (i40e_quiesce_vf_pci(vf))
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dev_err(&pf->pdev->dev, "VF %d PCI transactions stuck\n",
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dev_err(&pf->pdev->dev, "VF %d PCI transactions stuck\n",
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@@ -989,10 +993,6 @@ complete_reset:
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/* tell the VF the reset is done */
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/* tell the VF the reset is done */
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wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_id), I40E_VFR_VFACTIVE);
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wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_id), I40E_VFR_VFACTIVE);
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- /* clear the VFLR bit in GLGEN_VFLRSTAT */
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- reg_idx = (hw->func_caps.vf_base_id + vf->vf_id) / 32;
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- bit_idx = (hw->func_caps.vf_base_id + vf->vf_id) % 32;
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- wr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));
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i40e_flush(hw);
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i40e_flush(hw);
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clear_bit(__I40E_VF_DISABLE, &pf->state);
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clear_bit(__I40E_VF_DISABLE, &pf->state);
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}
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}
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@@ -1232,8 +1232,8 @@ static int i40e_vc_send_msg_to_vf(struct i40e_vf *vf, u32 v_opcode,
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/* single place to detect unsuccessful return values */
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/* single place to detect unsuccessful return values */
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if (v_retval) {
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if (v_retval) {
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vf->num_invalid_msgs++;
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vf->num_invalid_msgs++;
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- dev_err(&pf->pdev->dev, "VF %d failed opcode %d, error: %d\n",
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- vf->vf_id, v_opcode, v_retval);
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+ dev_info(&pf->pdev->dev, "VF %d failed opcode %d, retval: %d\n",
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+ vf->vf_id, v_opcode, v_retval);
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if (vf->num_invalid_msgs >
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if (vf->num_invalid_msgs >
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I40E_DEFAULT_NUM_INVALID_MSGS_ALLOWED) {
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I40E_DEFAULT_NUM_INVALID_MSGS_ALLOWED) {
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dev_err(&pf->pdev->dev,
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dev_err(&pf->pdev->dev,
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@@ -1251,9 +1251,9 @@ static int i40e_vc_send_msg_to_vf(struct i40e_vf *vf, u32 v_opcode,
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aq_ret = i40e_aq_send_msg_to_vf(hw, abs_vf_id, v_opcode, v_retval,
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aq_ret = i40e_aq_send_msg_to_vf(hw, abs_vf_id, v_opcode, v_retval,
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msg, msglen, NULL);
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msg, msglen, NULL);
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if (aq_ret) {
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if (aq_ret) {
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- dev_err(&pf->pdev->dev,
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- "Unable to send the message to VF %d aq_err %d\n",
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- vf->vf_id, pf->hw.aq.asq_last_status);
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+ dev_info(&pf->pdev->dev,
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+ "Unable to send the message to VF %d aq_err %d\n",
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+ vf->vf_id, pf->hw.aq.asq_last_status);
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return -EIO;
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return -EIO;
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}
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}
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@@ -1311,8 +1311,8 @@ static int i40e_vc_get_vf_resources_msg(struct i40e_vf *vf, u8 *msg)
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struct i40e_pf *pf = vf->pf;
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struct i40e_pf *pf = vf->pf;
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i40e_status aq_ret = 0;
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i40e_status aq_ret = 0;
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struct i40e_vsi *vsi;
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struct i40e_vsi *vsi;
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- int i = 0, len = 0;
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int num_vsis = 1;
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int num_vsis = 1;
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+ int len = 0;
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int ret;
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int ret;
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if (!test_bit(I40E_VF_STAT_INIT, &vf->vf_states)) {
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if (!test_bit(I40E_VF_STAT_INIT, &vf->vf_states)) {
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@@ -1374,15 +1374,14 @@ static int i40e_vc_get_vf_resources_msg(struct i40e_vf *vf, u8 *msg)
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vfres->num_queue_pairs = vf->num_queue_pairs;
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vfres->num_queue_pairs = vf->num_queue_pairs;
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vfres->max_vectors = pf->hw.func_caps.num_msix_vectors_vf;
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vfres->max_vectors = pf->hw.func_caps.num_msix_vectors_vf;
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if (vf->lan_vsi_idx) {
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if (vf->lan_vsi_idx) {
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- vfres->vsi_res[i].vsi_id = vf->lan_vsi_id;
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- vfres->vsi_res[i].vsi_type = I40E_VSI_SRIOV;
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- vfres->vsi_res[i].num_queue_pairs = vsi->alloc_queue_pairs;
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+ vfres->vsi_res[0].vsi_id = vf->lan_vsi_id;
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+ vfres->vsi_res[0].vsi_type = I40E_VSI_SRIOV;
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+ vfres->vsi_res[0].num_queue_pairs = vsi->alloc_queue_pairs;
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/* VFs only use TC 0 */
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/* VFs only use TC 0 */
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- vfres->vsi_res[i].qset_handle
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+ vfres->vsi_res[0].qset_handle
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= le16_to_cpu(vsi->info.qs_handle[0]);
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= le16_to_cpu(vsi->info.qs_handle[0]);
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- ether_addr_copy(vfres->vsi_res[i].default_mac_addr,
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+ ether_addr_copy(vfres->vsi_res[0].default_mac_addr,
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vf->default_lan_addr.addr);
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vf->default_lan_addr.addr);
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- i++;
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}
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}
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set_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states);
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set_bit(I40E_VF_STAT_ACTIVE, &vf->vf_states);
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@@ -2297,11 +2296,9 @@ int i40e_vc_process_vflr_event(struct i40e_pf *pf)
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/* read GLGEN_VFLRSTAT register to find out the flr VFs */
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/* read GLGEN_VFLRSTAT register to find out the flr VFs */
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vf = &pf->vf[vf_id];
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vf = &pf->vf[vf_id];
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reg = rd32(hw, I40E_GLGEN_VFLRSTAT(reg_idx));
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reg = rd32(hw, I40E_GLGEN_VFLRSTAT(reg_idx));
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- if (reg & BIT(bit_idx)) {
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+ if (reg & BIT(bit_idx))
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/* i40e_reset_vf will clear the bit in GLGEN_VFLRSTAT */
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/* i40e_reset_vf will clear the bit in GLGEN_VFLRSTAT */
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- if (!test_bit(__I40E_DOWN, &pf->state))
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- i40e_reset_vf(vf, true);
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- }
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+ i40e_reset_vf(vf, true);
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}
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}
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return 0;
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return 0;
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