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@@ -88,6 +88,10 @@ enum SCI_CLKS {
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#define SCI_SR(x) BIT((x) - 1)
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#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
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+#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
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+ SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
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+ SCI_SR(19) | SCI_SR(27)
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+
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#define min_sr(_port) ffs((_port)->sampling_rate_mask)
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#define max_sr(_port) fls((_port)->sampling_rate_mask)
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@@ -2179,6 +2183,17 @@ done:
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uart_update_timeout(port, termios->c_cflag, baud);
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if (best_clk >= 0) {
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+ if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
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+ switch (srr + 1) {
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+ case 5: smr_val |= SCSMR_SRC_5; break;
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+ case 7: smr_val |= SCSMR_SRC_7; break;
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+ case 11: smr_val |= SCSMR_SRC_11; break;
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+ case 13: smr_val |= SCSMR_SRC_13; break;
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+ case 16: smr_val |= SCSMR_SRC_16; break;
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+ case 17: smr_val |= SCSMR_SRC_17; break;
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+ case 19: smr_val |= SCSMR_SRC_19; break;
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+ case 27: smr_val |= SCSMR_SRC_27; break;
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+ }
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smr_val |= cks;
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dev_dbg(port->dev,
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"SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
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@@ -2227,6 +2242,16 @@ done:
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scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0);
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dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
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serial_port_out(port, SCSCR, scr_val);
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+ if ((srr + 1 == 5) &&
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+ (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
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+ /*
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+ * In asynchronous mode, when the sampling rate is 1/5, first
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+ * received data may become invalid on some SCIFA and SCIFB.
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+ * To avoid this problem wait more than 1 serial data time (1
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+ * bit time x serial data number) after setting SCSCR.RE = 1.
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+ */
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+ udelay(DIV_ROUND_UP(10 * 1000000, baud));
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+ }
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#ifdef CONFIG_SERIAL_SH_SCI_DMA
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/*
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@@ -2523,7 +2548,7 @@ static int sci_init_single(struct platform_device *dev,
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port->fifosize = 256;
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sci_port->overrun_reg = SCxSR;
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sci_port->overrun_mask = SCIFA_ORER;
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- sci_port->sampling_rate_mask = SCI_SR(16);
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+ sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
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break;
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case PORT_HSCIF:
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port->fifosize = 128;
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@@ -2535,7 +2560,7 @@ static int sci_init_single(struct platform_device *dev,
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port->fifosize = 64;
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sci_port->overrun_reg = SCxSR;
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sci_port->overrun_mask = SCIFA_ORER;
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- sci_port->sampling_rate_mask = SCI_SR(16);
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+ sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
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break;
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case PORT_SCIF:
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port->fifosize = 16;
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