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@@ -10,7 +10,6 @@ DEF_NATIVE(pv_mmu_ops, read_cr2, "mov %cr2, %eax");
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DEF_NATIVE(pv_mmu_ops, write_cr3, "mov %eax, %cr3");
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DEF_NATIVE(pv_mmu_ops, read_cr3, "mov %cr3, %eax");
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DEF_NATIVE(pv_cpu_ops, clts, "clts");
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-DEF_NATIVE(pv_cpu_ops, read_tsc, "rdtsc");
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#if defined(CONFIG_PARAVIRT_SPINLOCKS) && defined(CONFIG_QUEUED_SPINLOCKS)
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DEF_NATIVE(pv_lock_ops, queued_spin_unlock, "movb $0, (%eax)");
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@@ -52,7 +51,6 @@ unsigned native_patch(u8 type, u16 clobbers, void *ibuf,
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PATCH_SITE(pv_mmu_ops, read_cr3);
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PATCH_SITE(pv_mmu_ops, write_cr3);
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PATCH_SITE(pv_cpu_ops, clts);
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- PATCH_SITE(pv_cpu_ops, read_tsc);
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#if defined(CONFIG_PARAVIRT_SPINLOCKS) && defined(CONFIG_QUEUED_SPINLOCKS)
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case PARAVIRT_PATCH(pv_lock_ops.queued_spin_unlock):
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if (pv_is_native_spin_unlock()) {
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