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@@ -734,25 +734,9 @@ void intel_psr_flush(struct drm_device *dev,
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frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
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dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
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- if (HAS_DDI(dev)) {
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- /*
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- * By definition every flush should mean invalidate + flush,
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- * however on core platforms let's minimize the
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- * disable/re-enable so we can avoid the invalidate when flip
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- * originated the flush.
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- */
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- if (frontbuffer_bits && origin != ORIGIN_FLIP)
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- intel_psr_exit(dev);
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- } else {
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- /*
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- * On Valleyview and Cherryview we don't use hardware tracking
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- * so any plane updates or cursor moves don't result in a PSR
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- * invalidating. Which means we need to manually fake this in
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- * software for all flushes.
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- */
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- if (frontbuffer_bits)
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- intel_psr_exit(dev);
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- }
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+ /* By definition flush = invalidate + flush */
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+ if (frontbuffer_bits)
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+ intel_psr_exit(dev);
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if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
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if (!work_busy(&dev_priv->psr.work.work))
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