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@@ -45,6 +45,7 @@ enum clk_ids {
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CLK_S3,
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CLK_SDSRC,
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CLK_SSPSRC,
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+ CLK_RINT,
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/* Module Clocks */
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MOD_CLK_BASE
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@@ -94,10 +95,16 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
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DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
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+
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+ DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
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+ DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
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+
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+ DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
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};
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static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
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DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
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+ DEF_MOD("rwdt0", 402, R8A7796_CLK_R),
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DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
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};
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