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@@ -171,29 +171,33 @@ static int jz4780_nand_init_ecc(struct jz4780_nand_chip *nand, struct device *de
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chip->ecc.bytes = fls((1 + 8) * chip->ecc.size) *
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(chip->ecc.strength / 8);
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- if (nfc->bch && chip->ecc.mode == NAND_ECC_HW) {
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+ switch (chip->ecc.mode) {
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+ case NAND_ECC_HW:
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+ if (!nfc->bch) {
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+ dev_err(dev, "HW BCH selected, but BCH controller not found\n");
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+ return -ENODEV;
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+ }
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+
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chip->ecc.hwctl = jz4780_nand_ecc_hwctl;
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chip->ecc.calculate = jz4780_nand_ecc_calculate;
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chip->ecc.correct = jz4780_nand_ecc_correct;
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- } else if (!nfc->bch && chip->ecc.mode == NAND_ECC_HW) {
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- dev_err(dev, "HW BCH selected, but BCH controller not found\n");
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- return -ENODEV;
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- }
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-
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- if (chip->ecc.mode == NAND_ECC_HW_SYNDROME) {
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- dev_err(dev, "ECC HW syndrome not supported\n");
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- return -EINVAL;
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- }
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-
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- if (chip->ecc.mode != NAND_ECC_NONE)
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+ /* fall through */
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+ case NAND_ECC_SOFT:
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+ case NAND_ECC_SOFT_BCH:
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dev_info(dev, "using %s (strength %d, size %d, bytes %d)\n",
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(nfc->bch) ? "hardware BCH" : "software ECC",
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chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
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- else
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+ break;
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+ case NAND_ECC_NONE:
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dev_info(dev, "not using ECC\n");
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+ break;
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+ default:
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+ dev_err(dev, "ECC mode %d not supported\n", chip->ecc.mode);
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+ return -EINVAL;
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+ }
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- /* The NAND core will generate the ECC layout. */
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- if (chip->ecc.mode == NAND_ECC_SOFT || chip->ecc.mode == NAND_ECC_SOFT_BCH)
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+ /* The NAND core will generate the ECC layout for SW ECC */
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+ if (chip->ecc.mode != NAND_ECC_HW)
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return 0;
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/* Generate ECC layout. ECC codes are right aligned in the OOB area. */
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