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@@ -17,21 +17,23 @@ Further, syscon nodes that map platform-specific registers used for general
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system control is required:
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- compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
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- - compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
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+ - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
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+ "brcm,brcmstb-cpu-biu-ctrl",
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+ "syscon"
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- compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
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-hif-cpubiuctrl node
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+cpu-biu-ctrl node
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-------------------
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-SoCs with Broadcom Brahma15 ARM-based CPUs have a specific Bus Interface Unit
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-(BIU) block which controls and interfaces the CPU complex to the different
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-Memory Controller Ports (MCP), one per memory controller (MEMC). This BIU block
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-offers a feature called Write Pairing which consists in collapsing two adjacent
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-cache lines into a single (bursted) write transaction towards the memory
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-controller (MEMC) to maximize write bandwidth.
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+SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a
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+specific Bus Interface Unit (BIU) block which controls and interfaces the CPU
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+complex to the different Memory Controller Ports (MCP), one per memory
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+controller (MEMC). This BIU block offers a feature called Write Pairing which
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+consists in collapsing two adjacent cache lines into a single (bursted) write
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+transaction towards the memory controller (MEMC) to maximize write bandwidth.
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Required properties:
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- - compatible: must be "brcm,bcm7445-hif-cpubiuctrl", "syscon"
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+ - compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon"
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Optional properties:
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@@ -52,7 +54,7 @@ example:
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};
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hif_cpubiuctrl: syscon@3e2400 {
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- compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";
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+ compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon";
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reg = <0x3e2400 0x5b4>;
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brcm,write-pairing;
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};
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