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@@ -0,0 +1,75 @@
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+Renesas Gen3 DWC HDMI TX Encoder
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+================================
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+
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+The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
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+with a companion PHY IP.
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+
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+These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
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+Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
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+following device-specific properties.
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+
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+
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+Required properties:
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+
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+- compatible : Shall contain one or more of
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+ - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
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+ - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 compatible HDMI TX
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+
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+ When compatible with generic versions, nodes must list the SoC-specific
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+ version corresponding to the platform first, followed by the
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+ family-specific version.
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+
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+- reg: See dw_hdmi.txt.
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+- interrupts: HDMI interrupt number
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+- clocks: See dw_hdmi.txt.
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+- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
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+- ports: See dw_hdmi.txt. The DWC HDMI shall have one port numbered 0
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+ corresponding to the video input of the controller and one port numbered 1
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+ corresponding to its HDMI output. Each port shall have a single endpoint.
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+
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+Optional properties:
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+
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+- power-domains: Shall reference the power domain that contains the DWC HDMI,
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+ if any.
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+
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+
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+Example:
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+
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+ hdmi0: hdmi0@fead0000 {
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+ compatible = "renesas,r8a7795-dw-hdmi";
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+ reg = <0 0xfead0000 0 0x10000>;
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+ interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
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+ clock-names = "iahb", "isfr";
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+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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+ status = "disabled";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ port@0 {
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+ reg = <0>;
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+ dw_hdmi0_in: endpoint {
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+ remote-endpoint = <&du_out_hdmi0>;
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+ };
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+ };
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+ port@1 {
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+ reg = <1>;
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+ rcar_dw_hdmi0_out: endpoint {
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+ remote-endpoint = <&hdmi0_con>;
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+ };
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+ };
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+ };
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+ };
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+
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+ hdmi0-out {
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+ compatible = "hdmi-connector";
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+ label = "HDMI0 OUT";
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+ type = "a";
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+
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+ port {
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+ hdmi0_con: endpoint {
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+ remote-endpoint = <&rcar_dw_hdmi0_out>;
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+ };
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+ };
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+ };
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