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@@ -304,6 +304,7 @@ enum {
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MV5_LTMODE = 0x30,
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MV5_PHY_CTL = 0x0C,
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SATA_IFCFG = 0x050,
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+ LP_PHY_CTL = 0x058,
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MV_M2_PREAMP_MASK = 0x7e0,
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@@ -431,6 +432,7 @@ enum {
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MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
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MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
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MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
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+ MV_HP_FIX_LP_PHY_CTL = (1 << 13), /* fix speed in LP_PHY_CTL ? */
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/* Port private flags (pp_flags) */
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MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
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@@ -1358,6 +1360,7 @@ static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
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if (ofs != 0xffffffffU) {
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void __iomem *addr = mv_ap_base(link->ap) + ofs;
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+ struct mv_host_priv *hpriv = link->ap->host->private_data;
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if (sc_reg_in == SCR_CONTROL) {
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/*
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* Workaround for 88SX60x1 FEr SATA#26:
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@@ -1374,6 +1377,18 @@ static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
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*/
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if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
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val |= 0xf000;
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+
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+ if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) {
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+ void __iomem *lp_phy_addr =
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+ mv_ap_base(link->ap) + LP_PHY_CTL;
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+ /*
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+ * Set PHY speed according to SControl speed.
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+ */
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+ if ((val & 0xf0) == 0x10)
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+ writelfl(0x7, lp_phy_addr);
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+ else
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+ writelfl(0x227, lp_phy_addr);
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+ }
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}
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writelfl(val, addr);
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return 0;
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@@ -4110,6 +4125,15 @@ static int mv_platform_probe(struct platform_device *pdev)
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if (rc)
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goto err;
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+ /*
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+ * To allow disk hotplug on Armada 370/XP SoCs, the PHY speed must be
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+ * updated in the LP_PHY_CTL register.
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+ */
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+ if (pdev->dev.of_node &&
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+ of_device_is_compatible(pdev->dev.of_node,
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+ "marvell,armada-370-sata"))
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+ hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL;
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+
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/* initialize adapter */
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rc = mv_init_host(host);
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if (rc)
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