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@@ -710,64 +710,10 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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-/**
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- * mei_me_fw_status - retrieve fw status from the pci config space
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- *
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- * @dev: the device structure
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- * @fw_status: fw status registers storage
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- *
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- * returns 0 on success an error code otherwise
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- */
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-static int mei_me_fw_status(struct mei_device *dev,
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- struct mei_fw_status *fw_status)
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-{
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- const u32 pci_cfg_reg[] = {PCI_CFG_HFS_1, PCI_CFG_HFS_2};
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- int i;
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-
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- if (!fw_status)
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- return -EINVAL;
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-
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- switch (dev->pdev->device) {
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- case MEI_DEV_ID_IBXPK_1:
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- case MEI_DEV_ID_IBXPK_2:
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- case MEI_DEV_ID_CPT_1:
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- case MEI_DEV_ID_PBG_1:
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- case MEI_DEV_ID_PPT_1:
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- case MEI_DEV_ID_PPT_2:
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- case MEI_DEV_ID_PPT_3:
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- case MEI_DEV_ID_LPT_H:
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- case MEI_DEV_ID_LPT_W:
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- case MEI_DEV_ID_LPT_LP:
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- case MEI_DEV_ID_LPT_HR:
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- case MEI_DEV_ID_WPT_LP:
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- fw_status->count = 2;
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- break;
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- case MEI_DEV_ID_ICH10_1:
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- case MEI_DEV_ID_ICH10_2:
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- case MEI_DEV_ID_ICH10_3:
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- case MEI_DEV_ID_ICH10_4:
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- fw_status->count = 1;
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- break;
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- default:
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- fw_status->count = 0;
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- break;
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- }
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-
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- for (i = 0; i < fw_status->count && i < MEI_FW_STATUS_MAX; i++) {
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- int ret;
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- ret = pci_read_config_dword(dev->pdev,
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- pci_cfg_reg[i], &fw_status->status[i]);
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- if (ret)
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- return ret;
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- }
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- return 0;
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-}
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-
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static const struct mei_hw_ops mei_me_hw_ops = {
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.pg_state = mei_me_pg_state,
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- .fw_status = mei_me_fw_status,
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.host_is_ready = mei_me_host_is_ready,
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.hw_is_ready = mei_me_hw_is_ready,
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