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@@ -30,8 +30,29 @@
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#define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
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#define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
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#define ASPM_STATE_L1 (4) /* L1 state */
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+#define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
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+#define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
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+#define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
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+#define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
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+#define ASPM_STATE_L1_SS_PCIPM (ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM)
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+#define ASPM_STATE_L1_2_MASK (ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM)
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+#define ASPM_STATE_L1SS (ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\
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+ ASPM_STATE_L1_2_MASK)
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#define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
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-#define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1)
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+#define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
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+ ASPM_STATE_L1SS)
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+
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+/*
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+ * When L1 substates are enabled, the LTR L1.2 threshold is a timing parameter
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+ * that decides whether L1.1 or L1.2 is entered (Refer PCIe spec for details).
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+ * Not sure is there is a way to "calculate" this on the fly, but maybe we
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+ * could turn it into a parameter in future. This value has been taken from
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+ * the following files from Intel's coreboot (which is the only code I found
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+ * to have used this):
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+ * https://www.coreboot.org/pipermail/coreboot-gerrit/2015-March/021134.html
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+ * https://review.coreboot.org/#/c/8832/
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+ */
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+#define LTR_L1_2_THRESHOLD_BITS ((1 << 21) | (1 << 23) | (1 << 30))
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struct aspm_latency {
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u32 l0s; /* L0s latency (nsec) */
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@@ -40,6 +61,7 @@ struct aspm_latency {
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struct pcie_link_state {
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struct pci_dev *pdev; /* Upstream component of the Link */
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+ struct pci_dev *downstream; /* Downstream component, function 0 */
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struct pcie_link_state *root; /* pointer to the root port link */
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struct pcie_link_state *parent; /* pointer to the parent Link state */
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struct list_head sibling; /* node in link_list */
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@@ -47,11 +69,11 @@ struct pcie_link_state {
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struct list_head link; /* node in parent's children list */
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/* ASPM state */
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- u32 aspm_support:3; /* Supported ASPM state */
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- u32 aspm_enabled:3; /* Enabled ASPM state */
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- u32 aspm_capable:3; /* Capable ASPM state with latency */
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- u32 aspm_default:3; /* Default ASPM state by BIOS */
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- u32 aspm_disable:3; /* Disabled ASPM state */
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+ u32 aspm_support:7; /* Supported ASPM state */
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+ u32 aspm_enabled:7; /* Enabled ASPM state */
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+ u32 aspm_capable:7; /* Capable ASPM state with latency */
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+ u32 aspm_default:7; /* Default ASPM state by BIOS */
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+ u32 aspm_disable:7; /* Disabled ASPM state */
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/* Clock PM state */
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u32 clkpm_capable:1; /* Clock PM capable? */
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@@ -66,6 +88,14 @@ struct pcie_link_state {
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* has one slot under it, so at most there are 8 functions.
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*/
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struct aspm_latency acceptable[8];
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+
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+ /* L1 PM Substate info */
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+ struct {
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+ u32 up_cap_ptr; /* L1SS cap ptr in upstream dev */
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+ u32 dw_cap_ptr; /* L1SS cap ptr in downstream dev */
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+ u32 ctl1; /* value to be programmed in ctl1 */
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+ u32 ctl2; /* value to be programmed in ctl2 */
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+ } l1ss;
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};
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static int aspm_disabled, aspm_force;
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@@ -76,11 +106,14 @@ static LIST_HEAD(link_list);
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#define POLICY_DEFAULT 0 /* BIOS default setting */
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#define POLICY_PERFORMANCE 1 /* high performance */
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#define POLICY_POWERSAVE 2 /* high power saving */
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+#define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */
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#ifdef CONFIG_PCIEASPM_PERFORMANCE
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static int aspm_policy = POLICY_PERFORMANCE;
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#elif defined CONFIG_PCIEASPM_POWERSAVE
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static int aspm_policy = POLICY_POWERSAVE;
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+#elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE
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+static int aspm_policy = POLICY_POWER_SUPERSAVE;
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#else
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static int aspm_policy;
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#endif
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@@ -88,7 +121,8 @@ static int aspm_policy;
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static const char *policy_str[] = {
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[POLICY_DEFAULT] = "default",
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[POLICY_PERFORMANCE] = "performance",
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- [POLICY_POWERSAVE] = "powersave"
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+ [POLICY_POWERSAVE] = "powersave",
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+ [POLICY_POWER_SUPERSAVE] = "powersupersave"
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};
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#define LINK_RETRAIN_TIMEOUT HZ
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@@ -101,6 +135,9 @@ static int policy_to_aspm_state(struct pcie_link_state *link)
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return 0;
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case POLICY_POWERSAVE:
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/* Enable ASPM L0s/L1 */
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+ return (ASPM_STATE_L0S | ASPM_STATE_L1);
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+ case POLICY_POWER_SUPERSAVE:
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+ /* Enable Everything */
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return ASPM_STATE_ALL;
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case POLICY_DEFAULT:
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return link->aspm_default;
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@@ -115,7 +152,8 @@ static int policy_to_clkpm_state(struct pcie_link_state *link)
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/* Disable ASPM and Clock PM */
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return 0;
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case POLICY_POWERSAVE:
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- /* Disable Clock PM */
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+ case POLICY_POWER_SUPERSAVE:
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+ /* Enable Clock PM */
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return 1;
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case POLICY_DEFAULT:
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return link->clkpm_default;
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@@ -278,11 +316,33 @@ static u32 calc_l1_acceptable(u32 encoding)
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return (1000 << encoding);
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}
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+/* Convert L1SS T_pwr encoding to usec */
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+static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
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+{
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+ switch (scale) {
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+ case 0:
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+ return val * 2;
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+ case 1:
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+ return val * 10;
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+ case 2:
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+ return val * 100;
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+ }
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+ dev_err(&pdev->dev, "%s: Invalid T_PwrOn scale: %u\n",
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+ __func__, scale);
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+ return 0;
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+}
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+
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struct aspm_register_info {
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u32 support:2;
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u32 enabled:2;
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u32 latency_encoding_l0s;
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u32 latency_encoding_l1;
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+
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+ /* L1 substates */
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+ u32 l1ss_cap_ptr;
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+ u32 l1ss_cap;
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+ u32 l1ss_ctl1;
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+ u32 l1ss_ctl2;
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};
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static void pcie_get_aspm_reg(struct pci_dev *pdev,
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@@ -297,6 +357,22 @@ static void pcie_get_aspm_reg(struct pci_dev *pdev,
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info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
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pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16);
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info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
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+
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+ /* Read L1 PM substate capabilities */
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+ info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0;
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+ info->l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
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+ if (!info->l1ss_cap_ptr)
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+ return;
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+ pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CAP,
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+ &info->l1ss_cap);
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+ if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) {
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+ info->l1ss_cap = 0;
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+ return;
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+ }
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+ pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1,
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+ &info->l1ss_ctl1);
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+ pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2,
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+ &info->l1ss_ctl2);
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}
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static void pcie_aspm_check_latency(struct pci_dev *endpoint)
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@@ -327,6 +403,14 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
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* Check L1 latency.
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* Every switch on the path to root complex need 1
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* more microsecond for L1. Spec doesn't mention L0s.
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+ *
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+ * The exit latencies for L1 substates are not advertised
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+ * by a device. Since the spec also doesn't mention a way
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+ * to determine max latencies introduced by enabling L1
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+ * substates on the components, it is not clear how to do
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+ * a L1 substate exit latency check. We assume that the
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+ * L1 exit latencies advertised by a device include L1
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+ * substate latencies (and hence do not do any check).
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*/
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latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
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if ((link->aspm_capable & ASPM_STATE_L1) &&
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@@ -338,6 +422,60 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
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}
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}
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+/*
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+ * The L1 PM substate capability is only implemented in function 0 in a
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+ * multi function device.
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+ */
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+static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
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+{
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+ struct pci_dev *child;
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+
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+ list_for_each_entry(child, &linkbus->devices, bus_list)
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+ if (PCI_FUNC(child->devfn) == 0)
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+ return child;
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+ return NULL;
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+}
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+
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+/* Calculate L1.2 PM substate timing parameters */
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+static void aspm_calc_l1ss_info(struct pcie_link_state *link,
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+ struct aspm_register_info *upreg,
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+ struct aspm_register_info *dwreg)
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+{
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+ u32 val1, val2, scale1, scale2;
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+
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+ link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr;
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+ link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr;
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+ link->l1ss.ctl1 = link->l1ss.ctl2 = 0;
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+
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+ if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
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+ return;
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+
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+ /* Choose the greater of the two T_cmn_mode_rstr_time */
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+ val1 = (upreg->l1ss_cap >> 8) & 0xFF;
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+ val2 = (upreg->l1ss_cap >> 8) & 0xFF;
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+ if (val1 > val2)
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+ link->l1ss.ctl1 |= val1 << 8;
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+ else
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+ link->l1ss.ctl1 |= val2 << 8;
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+ /*
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+ * We currently use LTR L1.2 threshold to be fixed constant picked from
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+ * Intel's coreboot.
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+ */
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+ link->l1ss.ctl1 |= LTR_L1_2_THRESHOLD_BITS;
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+
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+ /* Choose the greater of the two T_pwr_on */
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+ val1 = (upreg->l1ss_cap >> 19) & 0x1F;
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+ scale1 = (upreg->l1ss_cap >> 16) & 0x03;
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+ val2 = (dwreg->l1ss_cap >> 19) & 0x1F;
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+ scale2 = (dwreg->l1ss_cap >> 16) & 0x03;
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+
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+ if (calc_l1ss_pwron(link->pdev, scale1, val1) >
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+ calc_l1ss_pwron(link->downstream, scale2, val2))
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+ link->l1ss.ctl2 |= scale1 | (val1 << 3);
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+ else
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+ link->l1ss.ctl2 |= scale2 | (val2 << 3);
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+}
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+
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static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
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{
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struct pci_dev *child, *parent = link->pdev;
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@@ -353,8 +491,9 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
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/* Get upstream/downstream components' register state */
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pcie_get_aspm_reg(parent, &upreg);
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- child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
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+ child = pci_function_0(linkbus);
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pcie_get_aspm_reg(child, &dwreg);
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+ link->downstream = child;
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/*
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* If ASPM not supported, don't mess with the clocks and link,
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@@ -397,6 +536,28 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
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link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);
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link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);
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+ /* Setup L1 substate */
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+ if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
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+ link->aspm_support |= ASPM_STATE_L1_1;
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+ if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
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+ link->aspm_support |= ASPM_STATE_L1_2;
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+ if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
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+ link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
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+ if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
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+ link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
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+
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+ if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
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+ link->aspm_enabled |= ASPM_STATE_L1_1;
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+ if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
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+ link->aspm_enabled |= ASPM_STATE_L1_2;
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+ if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
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+ link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
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+ if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
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+ link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
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+
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+ if (link->aspm_support & ASPM_STATE_L1SS)
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+ aspm_calc_l1ss_info(link, &upreg, &dwreg);
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+
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/* Save default state */
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link->aspm_default = link->aspm_enabled;
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@@ -435,6 +596,92 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
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}
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}
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+static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
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+ u32 clear, u32 set)
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+{
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+ u32 val;
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+
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+ pci_read_config_dword(pdev, pos, &val);
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+ val &= ~clear;
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+ val |= set;
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+ pci_write_config_dword(pdev, pos, val);
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+}
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+
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+/* Configure the ASPM L1 substates */
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+static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
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+{
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+ u32 val, enable_req;
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+ struct pci_dev *child = link->downstream, *parent = link->pdev;
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+ u32 up_cap_ptr = link->l1ss.up_cap_ptr;
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+ u32 dw_cap_ptr = link->l1ss.dw_cap_ptr;
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+
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+ enable_req = (link->aspm_enabled ^ state) & state;
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+
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+ /*
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+ * Here are the rules specified in the PCIe spec for enabling L1SS:
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+ * - When enabling L1.x, enable bit at parent first, then at child
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+ * - When disabling L1.x, disable bit at child first, then at parent
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+ * - When enabling ASPM L1.x, need to disable L1
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+ * (at child followed by parent).
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+ * - The ASPM/PCIPM L1.2 must be disabled while programming timing
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+ * parameters
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+ *
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+ * To keep it simple, disable all L1SS bits first, and later enable
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+ * what is needed.
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+ */
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+
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+ /* Disable all L1 substates */
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+ pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
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+ PCI_L1SS_CTL1_L1SS_MASK, 0);
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+ pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
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+ PCI_L1SS_CTL1_L1SS_MASK, 0);
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+ /*
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+ * If needed, disable L1, and it gets enabled later
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+ * in pcie_config_aspm_link().
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+ */
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+ if (enable_req & (ASPM_STATE_L1_1 | ASPM_STATE_L1_2)) {
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|
|
+ pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
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|
+ PCI_EXP_LNKCTL_ASPM_L1, 0);
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+ pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
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+ PCI_EXP_LNKCTL_ASPM_L1, 0);
|
|
|
+ }
|
|
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+
|
|
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+ if (enable_req & ASPM_STATE_L1_2_MASK) {
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|
|
+
|
|
|
+ /* Program T_pwr_on in both ports */
|
|
|
+ pci_write_config_dword(parent, up_cap_ptr + PCI_L1SS_CTL2,
|
|
|
+ link->l1ss.ctl2);
|
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+ pci_write_config_dword(child, dw_cap_ptr + PCI_L1SS_CTL2,
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|
+ link->l1ss.ctl2);
|
|
|
+
|
|
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+ /* Program T_cmn_mode in parent */
|
|
|
+ pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
|
|
|
+ 0xFF00, link->l1ss.ctl1);
|
|
|
+
|
|
|
+ /* Program LTR L1.2 threshold in both ports */
|
|
|
+ pci_clear_and_set_dword(parent, dw_cap_ptr + PCI_L1SS_CTL1,
|
|
|
+ 0xE3FF0000, link->l1ss.ctl1);
|
|
|
+ pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
|
|
|
+ 0xE3FF0000, link->l1ss.ctl1);
|
|
|
+ }
|
|
|
+
|
|
|
+ val = 0;
|
|
|
+ if (state & ASPM_STATE_L1_1)
|
|
|
+ val |= PCI_L1SS_CTL1_ASPM_L1_1;
|
|
|
+ if (state & ASPM_STATE_L1_2)
|
|
|
+ val |= PCI_L1SS_CTL1_ASPM_L1_2;
|
|
|
+ if (state & ASPM_STATE_L1_1_PCIPM)
|
|
|
+ val |= PCI_L1SS_CTL1_PCIPM_L1_1;
|
|
|
+ if (state & ASPM_STATE_L1_2_PCIPM)
|
|
|
+ val |= PCI_L1SS_CTL1_PCIPM_L1_2;
|
|
|
+
|
|
|
+ /* Enable what we need to enable */
|
|
|
+ pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
|
|
|
+ PCI_L1SS_CAP_L1_PM_SS, val);
|
|
|
+ pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
|
|
|
+ PCI_L1SS_CAP_L1_PM_SS, val);
|
|
|
+}
|
|
|
+
|
|
|
static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
|
|
|
{
|
|
|
pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
|
|
@@ -444,11 +691,23 @@ static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
|
|
|
static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
|
|
|
{
|
|
|
u32 upstream = 0, dwstream = 0;
|
|
|
- struct pci_dev *child, *parent = link->pdev;
|
|
|
+ struct pci_dev *child = link->downstream, *parent = link->pdev;
|
|
|
struct pci_bus *linkbus = parent->subordinate;
|
|
|
|
|
|
- /* Nothing to do if the link is already in the requested state */
|
|
|
+ /* Enable only the states that were not explicitly disabled */
|
|
|
state &= (link->aspm_capable & ~link->aspm_disable);
|
|
|
+
|
|
|
+ /* Can't enable any substates if L1 is not enabled */
|
|
|
+ if (!(state & ASPM_STATE_L1))
|
|
|
+ state &= ~ASPM_STATE_L1SS;
|
|
|
+
|
|
|
+ /* Spec says both ports must be in D0 before enabling PCI PM substates*/
|
|
|
+ if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
|
|
|
+ state &= ~ASPM_STATE_L1_SS_PCIPM;
|
|
|
+ state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Nothing to do if the link is already in the requested state */
|
|
|
if (link->aspm_enabled == state)
|
|
|
return;
|
|
|
/* Convert ASPM state to upstream/downstream ASPM register state */
|
|
@@ -460,6 +719,10 @@ static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
|
|
|
upstream |= PCI_EXP_LNKCTL_ASPM_L1;
|
|
|
dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
|
|
|
}
|
|
|
+
|
|
|
+ if (link->aspm_capable & ASPM_STATE_L1SS)
|
|
|
+ pcie_config_aspm_l1ss(link, state);
|
|
|
+
|
|
|
/*
|
|
|
* Spec 2.0 suggests all functions should be configured the
|
|
|
* same setting for ASPM. Enabling ASPM L1 should be done in
|
|
@@ -612,7 +875,8 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev)
|
|
|
* the BIOS's expectation, we'll do so once pci_enable_device() is
|
|
|
* called.
|
|
|
*/
|
|
|
- if (aspm_policy != POLICY_POWERSAVE) {
|
|
|
+ if (aspm_policy != POLICY_POWERSAVE &&
|
|
|
+ aspm_policy != POLICY_POWER_SUPERSAVE) {
|
|
|
pcie_config_aspm_path(link);
|
|
|
pcie_set_clkpm(link, policy_to_clkpm_state(link));
|
|
|
}
|
|
@@ -712,7 +976,8 @@ void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
|
|
|
if (aspm_disabled || !link)
|
|
|
return;
|
|
|
|
|
|
- if (aspm_policy != POLICY_POWERSAVE)
|
|
|
+ if (aspm_policy != POLICY_POWERSAVE &&
|
|
|
+ aspm_policy != POLICY_POWER_SUPERSAVE)
|
|
|
return;
|
|
|
|
|
|
down_read(&pci_bus_sem);
|