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@@ -248,6 +248,21 @@ static void setup_power_save(void)
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#endif
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}
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+static __init void initialize_cache_info(void)
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+{
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+ /*
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+ * Set cache line size based on type of cpu as a default.
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+ * Systems with OF can look in the properties on the cpu node(s)
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+ * for a possibly more accurate value.
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+ */
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+ dcache_bsize = cur_cpu_spec->dcache_bsize;
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+ icache_bsize = cur_cpu_spec->icache_bsize;
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+ ucache_bsize = 0;
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+ if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
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+ ucache_bsize = icache_bsize = dcache_bsize;
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+}
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+
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+
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/* Warning, IO base is not yet inited */
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void __init setup_arch(char **cmdline_p)
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{
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@@ -257,6 +272,7 @@ void __init setup_arch(char **cmdline_p)
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loops_per_jiffy = 500000000 / HZ;
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unflatten_device_tree();
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+ initialize_cache_info();
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check_for_initrd();
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probe_machine();
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@@ -272,17 +288,6 @@ void __init setup_arch(char **cmdline_p)
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xmon_setup();
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- /*
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- * Set cache line size based on type of cpu as a default.
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- * Systems with OF can look in the properties on the cpu node(s)
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- * for a possibly more accurate value.
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- */
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- dcache_bsize = cur_cpu_spec->dcache_bsize;
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- icache_bsize = cur_cpu_spec->icache_bsize;
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- ucache_bsize = 0;
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- if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
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- ucache_bsize = icache_bsize = dcache_bsize;
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-
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if (ppc_md.panic)
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setup_panic();
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