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@@ -243,17 +243,17 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_DSP_B:
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case SND_SOC_DAIFMT_AC97:
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- mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
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- mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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+ mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
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+ mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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break;
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default:
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/* configure a full-word SYNC pulse (LRCLK) */
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- mcasp_set_bits(mcasp->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
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- mcasp_set_bits(mcasp->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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+ mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
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+ mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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/* make 1st data bit occur one ACLK cycle after the frame sync */
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- mcasp_set_bits(mcasp->base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
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- mcasp_set_bits(mcasp->base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
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+ mcasp_set_bits(base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
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+ mcasp_set_bits(base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
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break;
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}
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