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@@ -8591,6 +8591,35 @@ static inline void mlxsw_reg_tnqcr_pack(char *payload)
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mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0);
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}
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+/* TNQDR - Tunneling NVE QoS Default Register
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+ * ------------------------------------------
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+ * The TNQDR register configures the default QoS settings for NVE
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+ * encapsulation.
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+ */
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+#define MLXSW_REG_TNQDR_ID 0xA011
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+#define MLXSW_REG_TNQDR_LEN 0x08
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+
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+MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN);
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+
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+/* reg_tnqdr_local_port
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+ * Local port number (receive port). CPU port is supported.
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+ * Access: Index
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+ */
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+MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8);
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+
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+/* reg_tnqdr_dscp
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+ * For encapsulation, the default DSCP.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
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+
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+static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port)
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+{
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+ MLXSW_REG_ZERO(tnqdr, payload);
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+ mlxsw_reg_tnqdr_local_port_set(payload, local_port);
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+ mlxsw_reg_tnqdr_dscp_set(payload, 0);
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+}
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+
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/* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register
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* --------------------------------------------------------
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* The TNEEM register maps ECN of the IP header at the ingress to the
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@@ -9274,6 +9303,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
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MLXSW_REG(tngcr),
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MLXSW_REG(tnumt),
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MLXSW_REG(tnqcr),
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+ MLXSW_REG(tnqdr),
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MLXSW_REG(tneem),
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MLXSW_REG(tndem),
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MLXSW_REG(tnpc),
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