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@@ -2095,6 +2095,8 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
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if (WARN_ON(!pll))
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return;
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+ mutex_lock(&dev_priv->dpll_lock);
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+
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if (IS_CANNONLAKE(dev_priv)) {
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/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
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val = I915_READ(DPCLKA_CFGCR0);
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@@ -2124,6 +2126,8 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
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} else if (INTEL_INFO(dev_priv)->gen < 9) {
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I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
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}
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+
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+ mutex_unlock(&dev_priv->dpll_lock);
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}
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static void intel_ddi_clk_disable(struct intel_encoder *encoder)
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