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@@ -21,65 +21,269 @@
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*
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*
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*/
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*/
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+#include <linux/types.h>
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+#include <linux/kernel.h>
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+#include <linux/slab.h>
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#include "pp_psm.h"
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#include "pp_psm.h"
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-#include "pp_psm_legacy.h"
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-#include "pp_psm_new.h"
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int psm_init_power_state_table(struct pp_hwmgr *hwmgr)
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int psm_init_power_state_table(struct pp_hwmgr *hwmgr)
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{
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{
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- if (hwmgr->chip_id != CHIP_VEGA12)
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- return psm_legacy_init_power_state_table(hwmgr);
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- else
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- return psm_new_init_power_state_table(hwmgr);
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+ int result;
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+ unsigned int i;
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+ unsigned int table_entries;
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+ struct pp_power_state *state;
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+ int size;
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+
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+ if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL)
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+ return 0;
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+
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+ if (hwmgr->hwmgr_func->get_power_state_size == NULL)
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+ return 0;
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+
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+ hwmgr->num_ps = table_entries = hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr);
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+
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+ hwmgr->ps_size = size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) +
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+ sizeof(struct pp_power_state);
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+
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+ if (table_entries == 0 || size == 0) {
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+ pr_warn("Please check whether power state management is suppported on this asic\n");
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+ return 0;
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+ }
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+
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+ hwmgr->ps = kzalloc(size * table_entries, GFP_KERNEL);
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+ if (hwmgr->ps == NULL)
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+ return -ENOMEM;
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+
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+ hwmgr->request_ps = kzalloc(size, GFP_KERNEL);
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+ if (hwmgr->request_ps == NULL) {
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+ kfree(hwmgr->ps);
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+ hwmgr->ps = NULL;
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+ return -ENOMEM;
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+ }
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+
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+ hwmgr->current_ps = kzalloc(size, GFP_KERNEL);
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+ if (hwmgr->current_ps == NULL) {
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+ kfree(hwmgr->request_ps);
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+ kfree(hwmgr->ps);
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+ hwmgr->request_ps = NULL;
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+ hwmgr->ps = NULL;
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+ return -ENOMEM;
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+ }
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+
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+ state = hwmgr->ps;
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+
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+ for (i = 0; i < table_entries; i++) {
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+ result = hwmgr->hwmgr_func->get_pp_table_entry(hwmgr, i, state);
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+
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+ if (state->classification.flags & PP_StateClassificationFlag_Boot) {
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+ hwmgr->boot_ps = state;
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+ memcpy(hwmgr->current_ps, state, size);
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+ memcpy(hwmgr->request_ps, state, size);
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+ }
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+
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+ state->id = i + 1; /* assigned unique num for every power state id */
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+
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+ if (state->classification.flags & PP_StateClassificationFlag_Uvd)
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+ hwmgr->uvd_ps = state;
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+ state = (struct pp_power_state *)((unsigned long)state + size);
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+ }
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+
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+ return 0;
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}
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}
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int psm_fini_power_state_table(struct pp_hwmgr *hwmgr)
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int psm_fini_power_state_table(struct pp_hwmgr *hwmgr)
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{
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{
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- if (hwmgr->chip_id != CHIP_VEGA12)
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- return psm_legacy_fini_power_state_table(hwmgr);
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- else
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- return psm_new_fini_power_state_table(hwmgr);
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+ if (hwmgr == NULL)
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+ return -EINVAL;
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+
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+ if (!hwmgr->ps)
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+ return 0;
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+
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+ kfree(hwmgr->current_ps);
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+ kfree(hwmgr->request_ps);
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+ kfree(hwmgr->ps);
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+ hwmgr->request_ps = NULL;
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+ hwmgr->ps = NULL;
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+ hwmgr->current_ps = NULL;
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+ return 0;
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+}
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+
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+static int psm_get_ui_state(struct pp_hwmgr *hwmgr,
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+ enum PP_StateUILabel ui_label,
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+ unsigned long *state_id)
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+{
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+ struct pp_power_state *state;
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+ int table_entries;
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+ int i;
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+
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+ table_entries = hwmgr->num_ps;
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+ state = hwmgr->ps;
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+
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+ for (i = 0; i < table_entries; i++) {
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+ if (state->classification.ui_label & ui_label) {
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+ *state_id = state->id;
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+ return 0;
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+ }
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+ state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
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+ }
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+ return -EINVAL;
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+}
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+
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+static int psm_get_state_by_classification(struct pp_hwmgr *hwmgr,
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+ enum PP_StateClassificationFlag flag,
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+ unsigned long *state_id)
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+{
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+ struct pp_power_state *state;
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+ int table_entries;
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+ int i;
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+
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+ table_entries = hwmgr->num_ps;
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+ state = hwmgr->ps;
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+
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+ for (i = 0; i < table_entries; i++) {
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+ if (state->classification.flags & flag) {
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+ *state_id = state->id;
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+ return 0;
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+ }
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+ state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
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+ }
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+ return -EINVAL;
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+}
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+
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+static int psm_set_states(struct pp_hwmgr *hwmgr, unsigned long state_id)
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+{
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+ struct pp_power_state *state;
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+ int table_entries;
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+ int i;
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+
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+ table_entries = hwmgr->num_ps;
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+
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+ state = hwmgr->ps;
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+
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+ for (i = 0; i < table_entries; i++) {
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+ if (state->id == state_id) {
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+ memcpy(hwmgr->request_ps, state, hwmgr->ps_size);
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+ return 0;
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+ }
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+ state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
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+ }
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+ return -EINVAL;
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}
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}
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int psm_set_boot_states(struct pp_hwmgr *hwmgr)
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int psm_set_boot_states(struct pp_hwmgr *hwmgr)
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{
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{
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- if (hwmgr->chip_id != CHIP_VEGA12)
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- return psm_legacy_set_boot_states(hwmgr);
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- else
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- return psm_new_set_boot_states(hwmgr);
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+ unsigned long state_id;
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+ int ret = -EINVAL;
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+
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+ if (!hwmgr->ps)
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+ return 0;
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+
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+ if (!psm_get_state_by_classification(hwmgr, PP_StateClassificationFlag_Boot,
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+ &state_id))
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+ ret = psm_set_states(hwmgr, state_id);
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+
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+ return ret;
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}
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}
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int psm_set_performance_states(struct pp_hwmgr *hwmgr)
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int psm_set_performance_states(struct pp_hwmgr *hwmgr)
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{
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{
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- if (hwmgr->chip_id != CHIP_VEGA12)
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- return psm_legacy_set_performance_states(hwmgr);
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- else
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- return psm_new_set_performance_states(hwmgr);
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+ unsigned long state_id;
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+ int ret = -EINVAL;
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+
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+ if (!hwmgr->ps)
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+ return 0;
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+
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+ if (!psm_get_ui_state(hwmgr, PP_StateUILabel_Performance,
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+ &state_id))
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+ ret = psm_set_states(hwmgr, state_id);
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+
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+ return ret;
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}
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}
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int psm_set_user_performance_state(struct pp_hwmgr *hwmgr,
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int psm_set_user_performance_state(struct pp_hwmgr *hwmgr,
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enum PP_StateUILabel label_id,
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enum PP_StateUILabel label_id,
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struct pp_power_state **state)
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struct pp_power_state **state)
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{
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{
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- if (hwmgr->chip_id != CHIP_VEGA12)
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- return psm_legacy_set_user_performance_state(hwmgr,
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- label_id,
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- state);
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+ int table_entries;
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+ int i;
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+
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+ if (!hwmgr->ps)
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+ return 0;
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+
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+ table_entries = hwmgr->num_ps;
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+ *state = hwmgr->ps;
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+
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+restart_search:
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+ for (i = 0; i < table_entries; i++) {
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+ if ((*state)->classification.ui_label & label_id)
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+ return 0;
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+ *state = (struct pp_power_state *)((uintptr_t)*state + hwmgr->ps_size);
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+ }
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+
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+ switch (label_id) {
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+ case PP_StateUILabel_Battery:
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+ case PP_StateUILabel_Balanced:
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+ label_id = PP_StateUILabel_Performance;
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+ goto restart_search;
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+ default:
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+ break;
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+ }
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+ return -EINVAL;
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+}
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+
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+static void power_state_management(struct pp_hwmgr *hwmgr,
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+ struct pp_power_state *new_ps)
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+{
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+ struct pp_power_state *pcurrent;
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+ struct pp_power_state *requested;
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+ bool equal;
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+
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+ if (new_ps != NULL)
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+ requested = new_ps;
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else
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else
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- return psm_new_set_user_performance_state(hwmgr,
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- label_id,
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- state);
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+ requested = hwmgr->request_ps;
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+
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+ pcurrent = hwmgr->current_ps;
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+
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+ phm_apply_state_adjust_rules(hwmgr, requested, pcurrent);
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+ if (pcurrent == NULL || (0 != phm_check_states_equal(hwmgr,
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+ &pcurrent->hardware, &requested->hardware, &equal)))
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+ equal = false;
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+
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+ if (!equal || phm_check_smc_update_required_for_display_configuration(hwmgr)) {
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+ phm_set_power_state(hwmgr, &pcurrent->hardware, &requested->hardware);
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+ memcpy(hwmgr->current_ps, hwmgr->request_ps, hwmgr->ps_size);
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+ }
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}
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}
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int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip,
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int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip,
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struct pp_power_state *new_ps)
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struct pp_power_state *new_ps)
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{
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{
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- if (hwmgr->chip_id != CHIP_VEGA12)
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- return psm_legacy_adjust_power_state_dynamic(hwmgr,
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- skip,
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- new_ps);
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- else
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- return psm_new_adjust_power_state_dynamic(hwmgr,
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- skip,
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- new_ps);
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+ uint32_t index;
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+ long workload;
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+
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+ if (skip)
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+ return 0;
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+
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+ phm_display_configuration_changed(hwmgr);
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+
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+ if (hwmgr->ps)
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+ power_state_management(hwmgr, new_ps);
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+
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+ phm_notify_smc_display_config_after_ps_adjustment(hwmgr);
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+
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+ if (!phm_force_dpm_levels(hwmgr, hwmgr->request_dpm_level))
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+ hwmgr->dpm_level = hwmgr->request_dpm_level;
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+
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+ if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
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+ index = fls(hwmgr->workload_mask);
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+ index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0;
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+ workload = hwmgr->workload_setting[index];
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+
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+ if (hwmgr->power_profile_mode != workload && hwmgr->hwmgr_func->set_power_profile_mode)
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+ hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
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+ }
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+
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+ return 0;
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}
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}
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+
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