drm/amd/display: fix hubp mpcc and opp tracking

This should be handled by mi and mpc only

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

@@ -686,6 +686,8 @@ void dce_mem_input_construct(
 	dce_mi->shifts = mi_shift;
 	dce_mi->masks = mi_mask;
 
+	dce_mi->base.mpcc_id = 0xf;
+	dce_mi->base.opp_id = 0xf;
 }
 
 void dce112_mem_input_construct(

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

@@ -1066,9 +1066,6 @@ static void plane_atomic_disable(struct dc *dc,
 			fe_idx);*/
 
 	mi->funcs->set_blank(mi, true);
-	/*todo: unhack this*/
-	mi->opp_id = 0xf;
-	mi->mpcc_id = 0xf;
 
 	if (dc->debug.sanity_checks)
 		verify_allow_pstate_change_high(dc->hwseq);
@@ -2304,7 +2301,8 @@ static void update_dchubp_dpp(
 		&plane_state->dcc,
 		plane_state->horizontal_mirror);
 
-	mi->funcs->set_blank(mi, !is_pipe_tree_visible(pipe_ctx));
+	if (is_pipe_tree_visible(pipe_ctx))
+		mi->funcs->set_blank(mi, false);
 }
 
 

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c

@@ -51,9 +51,8 @@ static void min10_set_blank(struct mem_input *mem_input, bool blank)
 		REG_WAIT(DCHUBP_CNTL,
 				HUBP_NO_OUTSTANDING_REQ, 1,
 				1, 200);
-		/*todo: unhack this
 		mem_input->mpcc_id = 0xf;
-		mem_input->opp_id = 0xf;*/
+		mem_input->opp_id = 0xf;
 	}
 }