|
@@ -256,8 +256,13 @@ static int edma_terminate_all(struct edma_chan *echan)
|
|
|
* echan->edesc is NULL and exit.)
|
|
|
*/
|
|
|
if (echan->edesc) {
|
|
|
+ int cyclic = echan->edesc->cyclic;
|
|
|
echan->edesc = NULL;
|
|
|
edma_stop(echan->ch_num);
|
|
|
+ /* Move the cyclic channel back to default queue */
|
|
|
+ if (cyclic)
|
|
|
+ edma_assign_channel_eventq(echan->ch_num,
|
|
|
+ EVENTQ_DEFAULT);
|
|
|
}
|
|
|
|
|
|
vchan_get_all_descriptors(&echan->vchan, &head);
|
|
@@ -724,6 +729,9 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
|
|
|
edesc->pset[i].param.opt |= TCINTEN;
|
|
|
}
|
|
|
|
|
|
+ /* Place the cyclic channel to highest priority queue */
|
|
|
+ edma_assign_channel_eventq(echan->ch_num, EVENTQ_0);
|
|
|
+
|
|
|
return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
|
|
|
}
|
|
|
|