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+/*
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+ * Copyright 2014 Tilera Corporation. All Rights Reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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+ * as published by the Free Software Foundation, version 2.
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+ *
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+ * This program is distributed in the hope that it will be useful, but
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+ * WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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+ * NON INFRINGEMENT. See the GNU General Public License for
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+ * more details.
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+ */
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+
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+#include <linux/errno.h>
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+#include <linux/spinlock.h>
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+#include <linux/module.h>
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+#include <linux/atomic.h>
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+#include <linux/interrupt.h>
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+
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+#include <asm/processor.h>
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+#include <asm/pmc.h>
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+
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+perf_irq_t perf_irq = NULL;
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+int handle_perf_interrupt(struct pt_regs *regs, int fault)
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+{
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+ int retval;
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+
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+ if (!perf_irq)
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+ panic("Unexpected PERF_COUNT interrupt %d\n", fault);
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+
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+ nmi_enter();
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+ retval = perf_irq(regs, fault);
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+ nmi_exit();
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+ return retval;
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+}
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+
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+/* Reserve PMC hardware if it is available. */
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+perf_irq_t reserve_pmc_hardware(perf_irq_t new_perf_irq)
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+{
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+ return cmpxchg(&perf_irq, NULL, new_perf_irq);
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+}
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+EXPORT_SYMBOL(reserve_pmc_hardware);
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+
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+/* Release PMC hardware. */
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+void release_pmc_hardware(void)
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+{
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+ perf_irq = NULL;
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+}
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+EXPORT_SYMBOL(release_pmc_hardware);
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+
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+
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+/*
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+ * Get current overflow status of each performance counter,
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+ * and auxiliary performance counter.
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+ */
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+unsigned long
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+pmc_get_overflow(void)
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+{
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+ unsigned long status;
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+
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+ /*
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+ * merge base+aux into a single vector
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+ */
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+ status = __insn_mfspr(SPR_PERF_COUNT_STS);
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+ status |= __insn_mfspr(SPR_AUX_PERF_COUNT_STS) << TILE_BASE_COUNTERS;
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+ return status;
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+}
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+
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+/*
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+ * Clear the status bit for the corresponding counter, if written
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+ * with a one.
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+ */
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+void
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+pmc_ack_overflow(unsigned long status)
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+{
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+ /*
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+ * clear overflow status by writing ones
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+ */
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+ __insn_mtspr(SPR_PERF_COUNT_STS, status);
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+ __insn_mtspr(SPR_AUX_PERF_COUNT_STS, status >> TILE_BASE_COUNTERS);
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+}
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+
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+/*
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+ * The perf count interrupts are masked and unmasked explicitly,
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+ * and only here. The normal irq_enable() does not enable them,
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+ * and irq_disable() does not disable them. That lets these
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+ * routines drive the perf count interrupts orthogonally.
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+ *
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+ * We also mask the perf count interrupts on entry to the perf count
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+ * interrupt handler in assembly code, and by default unmask them
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+ * again (with interrupt critical section protection) just before
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+ * returning from the interrupt. If the perf count handler returns
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+ * a non-zero error code, then we don't re-enable them before returning.
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+ *
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+ * For Pro, we rely on both interrupts being in the same word to update
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+ * them atomically so we never have one enabled and one disabled.
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+ */
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+
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+#if CHIP_HAS_SPLIT_INTR_MASK()
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+# if INT_PERF_COUNT < 32 || INT_AUX_PERF_COUNT < 32
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+# error Fix assumptions about which word PERF_COUNT interrupts are in
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+# endif
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+#endif
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+
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+static inline unsigned long long pmc_mask(void)
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+{
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+ unsigned long long mask = 1ULL << INT_PERF_COUNT;
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+ mask |= 1ULL << INT_AUX_PERF_COUNT;
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+ return mask;
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+}
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+
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+void unmask_pmc_interrupts(void)
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+{
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+ interrupt_mask_reset_mask(pmc_mask());
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+}
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+
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+void mask_pmc_interrupts(void)
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+{
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+ interrupt_mask_set_mask(pmc_mask());
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+}
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Zhigang Lu