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@@ -129,6 +129,62 @@ nv50_disp_super_iedt(struct nvkm_head *head, struct nvkm_outp *outp,
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return data;
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}
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+static void
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+nv50_disp_super_ied_on(struct nvkm_head *head,
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+ struct nvkm_ior *ior, int id, u32 khz)
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+{
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+ struct nvkm_subdev *subdev = &head->disp->engine.subdev;
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+ struct nvkm_bios *bios = subdev->device->bios;
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+ struct nvkm_outp *outp = ior->asy.outp;
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+ struct nvbios_ocfg iedtrs;
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+ struct nvbios_outp iedt;
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+ u8 ver, hdr, cnt, len, flags = 0x00;
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+ u32 data;
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+
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+ if (!outp) {
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+ IOR_DBG(ior, "nothing to attach");
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+ return;
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+ }
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+
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+ /* Lookup IED table for the device. */
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+ data = nv50_disp_super_iedt(head, outp, &ver, &hdr, &cnt, &len, &iedt);
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+ if (!data)
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+ return;
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+
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+ /* Lookup IEDT runtime settings for the current configuration. */
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+ if (ior->type == SOR) {
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+ if (ior->asy.proto == LVDS) {
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+ if (head->asy.or.depth == 24)
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+ flags |= 0x02;
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+ }
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+ if (ior->asy.link == 3)
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+ flags |= 0x01;
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+ }
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+
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+ data = nvbios_ocfg_match(bios, data, ior->asy.proto_evo, flags,
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+ &ver, &hdr, &cnt, &len, &iedtrs);
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+ if (!data) {
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+ OUTP_DBG(outp, "missing IEDT RS for %02x:%02x",
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+ ior->asy.proto_evo, flags);
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+ return;
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+ }
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+
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+ /* Execute the OnInt[23] script for the current frequency. */
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+ data = nvbios_oclk_match(bios, iedtrs.clkcmp[id], khz);
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+ if (!data) {
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+ OUTP_DBG(outp, "missing IEDT RSS %d for %02x:%02x %d khz",
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+ id, ior->asy.proto_evo, flags, khz);
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+ return;
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+ }
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+
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+ nvbios_init(subdev, data,
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+ init.outp = &outp->info;
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+ init.or = ior->id;
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+ init.link = ior->asy.link;
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+ init.head = head->id;
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+ );
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+}
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+
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static void
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nv50_disp_super_ied_off(struct nvkm_head *head, struct nvkm_ior *ior, int id)
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{
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@@ -154,6 +210,20 @@ nv50_disp_super_ied_off(struct nvkm_head *head, struct nvkm_ior *ior, int id)
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);
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}
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+static struct nvkm_ior *
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+nv50_disp_super_ior_asy(struct nvkm_head *head)
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+{
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+ struct nvkm_ior *ior;
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+ list_for_each_entry(ior, &head->disp->ior, head) {
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+ if (ior->asy.head & (1 << head->id)) {
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+ HEAD_DBG(head, "to %s", ior->name);
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+ return ior;
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+ }
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+ }
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+ HEAD_DBG(head, "nothing to attach");
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+ return NULL;
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+}
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+
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static struct nvkm_ior *
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nv50_disp_super_ior_arm(struct nvkm_head *head)
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{
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@@ -327,58 +397,40 @@ nv50_disp_intr_unk40_0(struct nv50_disp *disp, int head)
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}
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static void
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-nv50_disp_intr_unk20_2_dp(struct nv50_disp *disp, int head,
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- struct dcb_output *outp, u32 pclk)
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+nv50_disp_super_2_2_dp(struct nvkm_head *head, struct nvkm_ior *ior)
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{
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- struct nvkm_subdev *subdev = &disp->base.engine.subdev;
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- struct nvkm_device *device = subdev->device;
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- const int link = !(outp->sorconf.link & 1);
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- const int or = ffs(outp->or) - 1;
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- const u32 soff = ( or * 0x800);
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- const u32 loff = (link * 0x080) + soff;
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- const u32 ctrl = nvkm_rd32(device, 0x610794 + (or * 8));
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- const u32 symbol = 100000;
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- const s32 vactive = nvkm_rd32(device, 0x610af8 + (head * 0x540)) & 0xffff;
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- const s32 vblanke = nvkm_rd32(device, 0x610ae8 + (head * 0x540)) & 0xffff;
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- const s32 vblanks = nvkm_rd32(device, 0x610af0 + (head * 0x540)) & 0xffff;
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- u32 dpctrl = nvkm_rd32(device, 0x61c10c + loff);
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- u32 clksor = nvkm_rd32(device, 0x614300 + soff);
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+ struct nvkm_subdev *subdev = &head->disp->engine.subdev;
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+ const u32 khz = head->asy.hz / 1000;
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+ const u32 linkKBps = ior->dp.bw * 27000;
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+ const u32 symbol = 100000;
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int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
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int TU, VTUi, VTUf, VTUa;
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u64 link_data_rate, link_ratio, unk;
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u32 best_diff = 64 * symbol;
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- u32 link_nr, link_bw, bits;
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- u64 value;
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-
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- link_bw = (clksor & 0x000c0000) ? 270000 : 162000;
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- link_nr = hweight32(dpctrl & 0x000f0000);
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+ u64 h, v;
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/* symbols/hblank - algorithm taken from comments in tegra driver */
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- value = vblanke + vactive - vblanks - 7;
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- value = value * link_bw;
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- do_div(value, pclk);
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- value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr);
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- nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, value);
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+ h = head->asy.hblanke + head->asy.htotal - head->asy.hblanks - 7;
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+ h = h * linkKBps;
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+ do_div(h, khz);
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+ h = h - (3 * ior->dp.ef) - (12 / ior->dp.nr);
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/* symbols/vblank - algorithm taken from comments in tegra driver */
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- value = vblanks - vblanke - 25;
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- value = value * link_bw;
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- do_div(value, pclk);
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- value = value - ((36 / link_nr) + 3) - 1;
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- nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, value);
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+ v = head->asy.vblanks - head->asy.vblanke - 25;
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+ v = v * linkKBps;
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+ do_div(v, khz);
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+ v = v - ((36 / ior->dp.nr) + 3) - 1;
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- /* watermark / activesym */
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- if ((ctrl & 0xf0000) == 0x60000) bits = 30;
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- else if ((ctrl & 0xf0000) == 0x50000) bits = 24;
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- else bits = 18;
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+ ior->func->dp.audio_sym(ior, head->id, h, v);
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- link_data_rate = (pclk * bits / 8) / link_nr;
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+ /* watermark / activesym */
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+ link_data_rate = (khz * head->asy.or.depth / 8) / ior->dp.nr;
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/* calculate ratio of packed data rate to link symbol rate */
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link_ratio = link_data_rate * symbol;
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- do_div(link_ratio, link_bw);
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+ do_div(link_ratio, linkKBps);
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- for (TU = 64; TU >= 32; TU--) {
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+ for (TU = 64; ior->func->dp.activesym && TU >= 32; TU--) {
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/* calculate average number of valid symbols in each TU */
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u32 tu_valid = link_ratio * TU;
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u32 calc, diff;
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@@ -429,9 +481,15 @@ nv50_disp_intr_unk20_2_dp(struct nv50_disp *disp, int head,
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}
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}
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- if (!bestTU) {
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- nvkm_error(subdev, "unable to find suitable dp config\n");
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- return;
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+ if (ior->func->dp.activesym) {
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+ if (!bestTU) {
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+ nvkm_error(subdev, "unable to determine dp config\n");
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+ return;
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+ }
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+ ior->func->dp.activesym(ior, head->id, bestTU,
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+ bestVTUa, bestVTUf, bestVTUi);
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+ } else {
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+ bestTU = 64;
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}
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/* XXX close to vbios numbers, but not right */
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@@ -441,102 +499,61 @@ nv50_disp_intr_unk20_2_dp(struct nv50_disp *disp, int head,
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do_div(unk, symbol);
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unk += 6;
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- nvkm_mask(device, 0x61c10c + loff, 0x000001fc, bestTU << 2);
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- nvkm_mask(device, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 |
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- bestVTUf << 16 |
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- bestVTUi << 8 | unk);
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+ ior->func->dp.watermark(ior, head->id, unk);
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}
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-static void
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-nv50_disp_intr_unk20_2(struct nv50_disp *disp, int head)
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+void
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+nv50_disp_super_2_2(struct nv50_disp *disp, struct nvkm_head *head)
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{
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- struct nvkm_device *device = disp->base.engine.subdev.device;
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- struct nvkm_output *outp;
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- u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff;
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- u32 hval, hreg = 0x614200 + (head * 0x800);
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- u32 oval, oreg;
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- u32 mask, conf;
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+ const u32 khz = head->asy.hz / 1000;
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+ struct nvkm_outp *outp;
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+ struct nvkm_ior *ior;
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- outp = exec_clkcmp(disp, head, 0xff, pclk, &conf);
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- if (!outp)
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+ /* Determine which OR, if any, we're attaching from the head. */
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+ HEAD_DBG(head, "supervisor 2.2");
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+ ior = nv50_disp_super_ior_asy(head);
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+ if (!ior)
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return;
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- /* we allow both encoder attach and detach operations to occur
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- * within a single supervisor (ie. modeset) sequence. the
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- * encoder detach scripts quite often switch off power to the
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- * lanes, which requires the link to be re-trained.
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- *
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- * this is not generally an issue as the sink "must" (heh)
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- * signal an irq when it's lost sync so the driver can
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- * re-train.
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+ /* For some reason, NVIDIA decided not to:
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*
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- * however, on some boards, if one does not configure at least
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- * the gpu side of the link *before* attaching, then various
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- * things can go horribly wrong (PDISP disappearing from mmio,
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- * third supervisor never happens, etc).
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+ * A) Give dual-link LVDS a separate EVO protocol, like for TMDS.
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+ * and
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+ * B) Use SetControlOutputResource.PixelDepth on LVDS.
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*
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- * the solution is simply to retrain here, if necessary. last
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- * i checked, the binary driver userspace does not appear to
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- * trigger this situation (it forces an UPDATE between steps).
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+ * Override the values we usually read from HW with the same
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+ * data we pass though an ioctl instead.
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*/
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- if (outp->info.type == DCB_OUTPUT_DP) {
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- u32 soff = (ffs(outp->info.or) - 1) * 0x08;
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- u32 ctrl, datarate;
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-
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- if (outp->info.location == 0) {
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- ctrl = nvkm_rd32(device, 0x610794 + soff);
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- soff = 1;
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- } else {
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- ctrl = nvkm_rd32(device, 0x610b80 + soff);
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- soff = 2;
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- }
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-
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- switch ((ctrl & 0x000f0000) >> 16) {
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- case 6: datarate = pclk * 30; break;
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- case 5: datarate = pclk * 24; break;
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- case 2:
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- default:
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- datarate = pclk * 18;
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- break;
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- }
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-
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- if (nvkm_output_dp_train(outp, datarate / soff))
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- OUTP_ERR(outp, "link not trained before attach");
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+ if (ior->type == SOR && ior->asy.proto == LVDS) {
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+ head->asy.or.depth = (disp->sor.lvdsconf & 0x0200) ? 24 : 18;
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+ ior->asy.link = (disp->sor.lvdsconf & 0x0100) ? 3 : 1;
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}
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- exec_clkcmp(disp, head, 0, pclk, &conf);
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+ /* Handle any link training, etc. */
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+ if ((outp = ior->asy.outp) && outp->func->acquire)
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+ outp->func->acquire(outp);
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- if (!outp->info.location && outp->info.type == DCB_OUTPUT_ANALOG) {
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- oreg = 0x614280 + (ffs(outp->info.or) - 1) * 0x800;
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- oval = 0x00000000;
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- hval = 0x00000000;
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- mask = 0xffffffff;
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- } else
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- if (!outp->info.location) {
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- if (outp->info.type == DCB_OUTPUT_DP)
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- nv50_disp_intr_unk20_2_dp(disp, head, &outp->info, pclk);
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- oreg = 0x614300 + (ffs(outp->info.or) - 1) * 0x800;
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- oval = (conf & 0x0100) ? 0x00000101 : 0x00000000;
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- hval = 0x00000000;
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- mask = 0x00000707;
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- } else {
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- oreg = 0x614380 + (ffs(outp->info.or) - 1) * 0x800;
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- oval = 0x00000001;
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- hval = 0x00000001;
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- mask = 0x00000707;
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- }
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+ /* Execute OnInt2 IED script. */
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+ nv50_disp_super_ied_on(head, ior, 0, khz);
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+
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+ /* Program RG clock divider. */
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+ head->func->rgclk(head, ior->asy.rgdiv);
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- nvkm_mask(device, hreg, 0x0000000f, hval);
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- nvkm_mask(device, oreg, mask, oval);
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+ /* Mode-specific internal DP configuration. */
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+ if (ior->type == SOR && ior->asy.proto == DP)
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+ nv50_disp_super_2_2_dp(head, ior);
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- nv50_disp_dptmds_war_2(disp, &outp->info);
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+ /* OR-specific handling. */
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+ ior->func->clock(ior);
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+ if (ior->func->war_2)
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+ ior->func->war_2(ior);
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}
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void
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nv50_disp_super_2_1(struct nv50_disp *disp, struct nvkm_head *head)
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{
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struct nvkm_devinit *devinit = disp->base.engine.subdev.device->devinit;
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- u32 khz = head->asy.hz / 1000;
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+ const u32 khz = head->asy.hz / 1000;
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HEAD_DBG(head, "supervisor 2.1 - %d khz", khz);
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if (khz)
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nvkm_devinit_pll_set(devinit, PLL_VPLL0 + head->id, khz);
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@@ -636,7 +653,7 @@ nv50_disp_super(struct work_struct *work)
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list_for_each_entry(head, &disp->base.head, head) {
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if (!(super & (0x00000080 << head->id)))
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continue;
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- nv50_disp_intr_unk20_2(disp, head->id);
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+ nv50_disp_super_2_2(disp, head);
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}
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} else
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if (disp->super & 0x00000040) {
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Ben Skeggs