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@@ -777,6 +777,7 @@ exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata,
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{
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struct samsung_retention_ctrl *ctrl;
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struct regmap *pmu_regs;
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+ int i;
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ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);
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if (!ctrl)
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@@ -794,6 +795,10 @@ exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata,
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ctrl->enable = exynos_retention_enable;
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ctrl->disable = exynos_retention_disable;
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+ /* Ensure that retention is disabled on driver init */
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+ for (i = 0; i < ctrl->nr_regs; i++)
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+ regmap_write(pmu_regs, ctrl->regs[i], ctrl->value);
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+
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return ctrl;
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}
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@@ -1546,6 +1551,54 @@ static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst =
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EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
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};
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+/* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */
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+static const u32 exynos5433_retention_regs[] = {
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+ EXYNOS5433_PAD_RETENTION_TOP_OPTION,
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+ EXYNOS5433_PAD_RETENTION_UART_OPTION,
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+ EXYNOS5433_PAD_RETENTION_EBIA_OPTION,
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+ EXYNOS5433_PAD_RETENTION_EBIB_OPTION,
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+ EXYNOS5433_PAD_RETENTION_SPI_OPTION,
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+ EXYNOS5433_PAD_RETENTION_MIF_OPTION,
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+ EXYNOS5433_PAD_RETENTION_USBXTI_OPTION,
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+ EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION,
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+ EXYNOS5433_PAD_RETENTION_UFS_OPTION,
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+ EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION,
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+};
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+
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+static const struct samsung_retention_data exynos5433_retention_data __initconst = {
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+ .regs = exynos5433_retention_regs,
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+ .nr_regs = ARRAY_SIZE(exynos5433_retention_regs),
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+ .value = EXYNOS_WAKEUP_FROM_LOWPWR,
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+ .refcnt = &exynos_shared_retention_refcnt,
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+ .init = exynos_retention_init,
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+};
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+
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+/* PMU retention control for audio pins can be tied to audio pin bank */
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+static const u32 exynos5433_audio_retention_regs[] = {
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+ EXYNOS5433_PAD_RETENTION_AUD_OPTION,
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+};
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+
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+static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = {
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+ .regs = exynos5433_audio_retention_regs,
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+ .nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs),
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+ .value = EXYNOS_WAKEUP_FROM_LOWPWR,
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+ .init = exynos_retention_init,
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+};
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+
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+/* PMU retention control for mmc pins can be tied to fsys pin bank */
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+static const u32 exynos5433_fsys_retention_regs[] = {
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+ EXYNOS5433_PAD_RETENTION_MMC0_OPTION,
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+ EXYNOS5433_PAD_RETENTION_MMC1_OPTION,
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+ EXYNOS5433_PAD_RETENTION_MMC2_OPTION,
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+};
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+
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+static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = {
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+ .regs = exynos5433_fsys_retention_regs,
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+ .nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs),
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+ .value = EXYNOS_WAKEUP_FROM_LOWPWR,
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+ .init = exynos_retention_init,
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+};
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+
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/*
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* Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
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* ten gpio/pin-mux/pinconfig controllers.
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@@ -1559,6 +1612,7 @@ const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = {
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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.nr_ext_resources = 1,
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+ .retention_data = &exynos5433_retention_data,
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}, {
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/* pin-controller instance 1 data */
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.pin_banks = exynos5433_pin_banks1,
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@@ -1566,6 +1620,7 @@ const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = {
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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+ .retention_data = &exynos5433_audio_retention_data,
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}, {
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/* pin-controller instance 2 data */
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.pin_banks = exynos5433_pin_banks2,
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@@ -1573,6 +1628,7 @@ const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = {
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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+ .retention_data = &exynos5433_retention_data,
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}, {
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/* pin-controller instance 3 data */
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.pin_banks = exynos5433_pin_banks3,
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@@ -1580,6 +1636,7 @@ const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = {
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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+ .retention_data = &exynos5433_retention_data,
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}, {
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/* pin-controller instance 4 data */
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.pin_banks = exynos5433_pin_banks4,
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@@ -1587,6 +1644,7 @@ const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = {
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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+ .retention_data = &exynos5433_retention_data,
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}, {
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/* pin-controller instance 5 data */
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.pin_banks = exynos5433_pin_banks5,
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@@ -1594,6 +1652,7 @@ const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = {
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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+ .retention_data = &exynos5433_fsys_retention_data,
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}, {
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/* pin-controller instance 6 data */
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.pin_banks = exynos5433_pin_banks6,
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@@ -1601,6 +1660,7 @@ const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = {
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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+ .retention_data = &exynos5433_retention_data,
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}, {
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/* pin-controller instance 7 data */
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.pin_banks = exynos5433_pin_banks7,
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@@ -1608,6 +1668,7 @@ const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = {
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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+ .retention_data = &exynos5433_retention_data,
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}, {
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/* pin-controller instance 8 data */
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.pin_banks = exynos5433_pin_banks8,
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@@ -1615,6 +1676,7 @@ const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = {
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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+ .retention_data = &exynos5433_retention_data,
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}, {
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/* pin-controller instance 9 data */
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.pin_banks = exynos5433_pin_banks9,
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@@ -1622,6 +1684,7 @@ const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = {
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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+ .retention_data = &exynos5433_retention_data,
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},
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};
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