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@@ -1,5 +1,5 @@
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/* Intel(R) Gigabit Ethernet Linux driver
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- * Copyright(c) 2007-2014 Intel Corporation.
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+ * Copyright(c) 2007-2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -1900,8 +1900,8 @@ static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
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* igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
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* @hw: pointer to the HW structure
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*
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- * After rx enable if managability is enabled then there is likely some
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- * bad data at the start of the fifo and possibly in the DMA fifo. This
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+ * After rx enable if manageability is enabled then there is likely some
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+ * bad data at the start of the fifo and possibly in the DMA fifo. This
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* function clears the fifos and flushes any packets that came in as rx was
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* being enabled.
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**/
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@@ -1910,6 +1910,11 @@ void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
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u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
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int i, ms_wait;
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+ /* disable IPv6 options as per hardware errata */
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+ rfctl = rd32(E1000_RFCTL);
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+ rfctl |= E1000_RFCTL_IPV6_EX_DIS;
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+ wr32(E1000_RFCTL, rfctl);
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+
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if (hw->mac.type != e1000_82575 ||
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!(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
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return;
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@@ -1937,7 +1942,6 @@ void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
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* incoming packets are rejected. Set enable and wait 2ms so that
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* any packet that was coming in as RCTL.EN was set is flushed
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*/
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- rfctl = rd32(E1000_RFCTL);
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wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
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rlpml = rd32(E1000_RLPML);
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