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@@ -1923,6 +1923,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
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adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
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adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
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WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
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WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
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}
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}
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+ break;
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case CHIP_FIJI:
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case CHIP_FIJI:
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for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
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for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
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switch (reg_offset) {
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switch (reg_offset) {
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