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@@ -241,24 +241,23 @@ static int _mv88e6xxx_phy_write(struct mv88e6xxx_priv_state *ps, int addr,
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return 0;
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}
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-#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
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static int mv88e6xxx_ppu_disable(struct mv88e6xxx_priv_state *ps)
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{
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int ret;
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unsigned long timeout;
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- ret = mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL);
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+ ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL);
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if (ret < 0)
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return ret;
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- ret = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
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- ret & ~GLOBAL_CONTROL_PPU_ENABLE);
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+ ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
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+ ret & ~GLOBAL_CONTROL_PPU_ENABLE);
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if (ret)
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return ret;
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timeout = jiffies + 1 * HZ;
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while (time_before(jiffies, timeout)) {
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- ret = mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS);
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+ ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS);
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if (ret < 0)
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return ret;
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@@ -361,35 +360,33 @@ void mv88e6xxx_ppu_state_init(struct mv88e6xxx_priv_state *ps)
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ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
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}
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-int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
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+static int mv88e6xxx_phy_read_ppu(struct mv88e6xxx_priv_state *ps, int addr,
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+ int regnum)
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{
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- struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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int ret;
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ret = mv88e6xxx_ppu_access_get(ps);
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if (ret >= 0) {
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- ret = mv88e6xxx_reg_read(ps, addr, regnum);
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+ ret = _mv88e6xxx_reg_read(ps, addr, regnum);
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mv88e6xxx_ppu_access_put(ps);
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}
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return ret;
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}
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-int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
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- int regnum, u16 val)
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+static int mv88e6xxx_phy_write_ppu(struct mv88e6xxx_priv_state *ps, int addr,
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+ int regnum, u16 val)
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{
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- struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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int ret;
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ret = mv88e6xxx_ppu_access_get(ps);
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if (ret >= 0) {
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- ret = mv88e6xxx_reg_write(ps, addr, regnum, val);
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+ ret = _mv88e6xxx_reg_write(ps, addr, regnum, val);
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mv88e6xxx_ppu_access_put(ps);
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}
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return ret;
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}
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-#endif
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static bool mv88e6xxx_6065_family(struct mv88e6xxx_priv_state *ps)
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{
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@@ -2599,6 +2596,9 @@ int mv88e6xxx_setup_common(struct mv88e6xxx_priv_state *ps)
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INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
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+ if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
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+ mv88e6xxx_ppu_state_init(ps);
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+
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return 0;
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}
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@@ -2884,7 +2884,12 @@ mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
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return 0xffff;
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mutex_lock(&ps->smi_mutex);
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- ret = _mv88e6xxx_phy_read(ps, addr, regnum);
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+
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+ if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
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+ ret = mv88e6xxx_phy_read_ppu(ps, addr, regnum);
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+ else
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+ ret = _mv88e6xxx_phy_read(ps, addr, regnum);
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+
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mutex_unlock(&ps->smi_mutex);
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return ret;
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}
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@@ -2900,7 +2905,12 @@ mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
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return 0xffff;
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mutex_lock(&ps->smi_mutex);
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- ret = _mv88e6xxx_phy_write(ps, addr, regnum, val);
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+
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+ if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
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+ ret = mv88e6xxx_phy_write_ppu(ps, addr, regnum, val);
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+ else
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+ ret = _mv88e6xxx_phy_write(ps, addr, regnum, val);
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+
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mutex_unlock(&ps->smi_mutex);
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return ret;
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}
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