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@@ -52,8 +52,10 @@
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#define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14)
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#define SATA_TOP_CTRL_PHY_OFFS 0x8
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#define SATA_TOP_MAX_PHYS 2
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-#define SATA_TOP_CTRL_SATA_TP_OUT 0x1c
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-#define SATA_TOP_CTRL_CLIENT_INIT_CTRL 0x20
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+
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+#define SATA_FIRST_PORT_CTRL 0x700
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+#define SATA_NEXT_PORT_CTRL_OFFSET 0x80
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+#define SATA_PORT_PCTRL6(reg_base) (reg_base + 0x18)
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/* On big-endian MIPS, buses are reversed to big endian, so switch them back */
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#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
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@@ -69,14 +71,21 @@
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(DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) | \
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(MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))
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+enum brcm_ahci_quirks {
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+ BRCM_AHCI_QUIRK_NO_NCQ = BIT(0),
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+ BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(1),
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+};
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+
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struct brcm_ahci_priv {
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struct device *dev;
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void __iomem *top_ctrl;
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u32 port_mask;
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+ u32 quirks;
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};
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static const struct ata_port_info ahci_brcm_port_info = {
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- .flags = AHCI_FLAG_COMMON,
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+ .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
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+ .link_flags = ATA_LFLAG_NO_DB_DELAY,
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.pio_mask = ATA_PIO4,
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_platform_ops,
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@@ -107,6 +116,34 @@ static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
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writel_relaxed(val, addr);
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}
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+static void brcm_sata_alpm_init(struct ahci_host_priv *hpriv)
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+{
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+ struct brcm_ahci_priv *priv = hpriv->plat_data;
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+ u32 bus_ctrl, port_ctrl, host_caps;
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+ int i;
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+
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+ /* Enable support for ALPM */
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+ bus_ctrl = brcm_sata_readreg(priv->top_ctrl +
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+ SATA_TOP_CTRL_BUS_CTRL);
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+ brcm_sata_writereg(bus_ctrl | OVERRIDE_HWINIT,
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+ priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
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+ host_caps = readl(hpriv->mmio + HOST_CAP);
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+ writel(host_caps | HOST_CAP_ALPM, hpriv->mmio);
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+ brcm_sata_writereg(bus_ctrl, priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
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+
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+ /*
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+ * Adjust timeout to allow PLL sufficient time to lock while waking
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+ * up from slumber mode.
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+ */
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+ for (i = 0, port_ctrl = SATA_FIRST_PORT_CTRL;
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+ i < SATA_TOP_MAX_PHYS;
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+ i++, port_ctrl += SATA_NEXT_PORT_CTRL_OFFSET) {
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+ if (priv->port_mask & BIT(i))
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+ writel(0xff1003fc,
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+ hpriv->mmio + SATA_PORT_PCTRL6(port_ctrl));
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+ }
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+}
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+
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static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
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{
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void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
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@@ -114,6 +151,9 @@ static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
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void __iomem *p;
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u32 reg;
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+ if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
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+ return;
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+
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/* clear PHY_DEFAULT_POWER_STATE */
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p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
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reg = brcm_sata_readreg(p);
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@@ -143,6 +183,9 @@ static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
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void __iomem *p;
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u32 reg;
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+ if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
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+ return;
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+
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/* power-off the PHY digital logic */
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p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
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reg = brcm_sata_readreg(p);
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@@ -230,6 +273,7 @@ static int brcm_ahci_resume(struct device *dev)
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brcm_sata_init(priv);
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brcm_sata_phys_enable(priv);
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+ brcm_sata_alpm_init(hpriv);
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return ahci_platform_resume(dev);
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}
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#endif
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@@ -256,6 +300,11 @@ static int brcm_ahci_probe(struct platform_device *pdev)
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if (IS_ERR(priv->top_ctrl))
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return PTR_ERR(priv->top_ctrl);
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+ if (of_device_is_compatible(dev->of_node, "brcm,bcm7425-ahci")) {
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+ priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ;
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+ priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
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+ }
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+
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brcm_sata_init(priv);
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priv->port_mask = brcm_ahci_get_portmask(pdev, priv);
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@@ -269,10 +318,15 @@ static int brcm_ahci_probe(struct platform_device *pdev)
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return PTR_ERR(hpriv);
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hpriv->plat_data = priv;
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+ brcm_sata_alpm_init(hpriv);
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+
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ret = ahci_platform_enable_resources(hpriv);
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if (ret)
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return ret;
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+ if (priv->quirks & BRCM_AHCI_QUIRK_NO_NCQ)
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+ hpriv->flags |= AHCI_HFLAG_NO_NCQ;
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+
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ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
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&ahci_platform_sht);
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if (ret)
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@@ -300,6 +354,7 @@ static int brcm_ahci_remove(struct platform_device *pdev)
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}
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static const struct of_device_id ahci_of_match[] = {
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+ {.compatible = "brcm,bcm7425-ahci"},
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{.compatible = "brcm,bcm7445-ahci"},
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{},
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};
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