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@@ -91,23 +91,24 @@
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#define NFP_NET_RSS_IPV6_EX_UDP 9
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/**
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- * @NFP_NET_TXR_MAX: Maximum number of TX rings
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- * @NFP_NET_RXR_MAX: Maximum number of RX rings
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+ * Ring counts
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+ * %NFP_NET_TXR_MAX: Maximum number of TX rings
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+ * %NFP_NET_RXR_MAX: Maximum number of RX rings
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*/
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#define NFP_NET_TXR_MAX 64
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#define NFP_NET_RXR_MAX 64
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/**
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* Read/Write config words (0x0000 - 0x002c)
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- * @NFP_NET_CFG_CTRL: Global control
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- * @NFP_NET_CFG_UPDATE: Indicate which fields are updated
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- * @NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings
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- * @NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings
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- * @NFP_NET_CFG_MTU: Set MTU size
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- * @NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU)
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- * @NFP_NET_CFG_EXN: MSI-X table entry for exceptions
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- * @NFP_NET_CFG_LSC: MSI-X table entry for link state changes
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- * @NFP_NET_CFG_MACADDR: MAC address
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+ * %NFP_NET_CFG_CTRL: Global control
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+ * %NFP_NET_CFG_UPDATE: Indicate which fields are updated
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+ * %NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings
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+ * %NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings
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+ * %NFP_NET_CFG_MTU: Set MTU size
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+ * %NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU)
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+ * %NFP_NET_CFG_EXN: MSI-X table entry for exceptions
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+ * %NFP_NET_CFG_LSC: MSI-X table entry for link state changes
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+ * %NFP_NET_CFG_MACADDR: MAC address
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*
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* TODO:
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* - define Error details in UPDATE
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@@ -176,14 +177,14 @@
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/**
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* Read-only words (0x0030 - 0x0050):
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- * @NFP_NET_CFG_VERSION: Firmware version number
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- * @NFP_NET_CFG_STS: Status
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- * @NFP_NET_CFG_CAP: Capabilities (same bits as @NFP_NET_CFG_CTRL)
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- * @NFP_NET_CFG_MAX_TXRINGS: Maximum number of TX rings
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- * @NFP_NET_CFG_MAX_RXRINGS: Maximum number of RX rings
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- * @NFP_NET_CFG_MAX_MTU: Maximum support MTU
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- * @NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only)
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- * @NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only)
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+ * %NFP_NET_CFG_VERSION: Firmware version number
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+ * %NFP_NET_CFG_STS: Status
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+ * %NFP_NET_CFG_CAP: Capabilities (same bits as %NFP_NET_CFG_CTRL)
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+ * %NFP_NET_CFG_MAX_TXRINGS: Maximum number of TX rings
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+ * %NFP_NET_CFG_MAX_RXRINGS: Maximum number of RX rings
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+ * %NFP_NET_CFG_MAX_MTU: Maximum support MTU
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+ * %NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only)
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+ * %NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only)
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*
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* TODO:
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* - define more STS bits
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@@ -228,31 +229,31 @@
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/**
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* RSS capabilities
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- * @NFP_NET_CFG_RSS_CAP_HFUNC: supported hash functions (same bits as
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- * @NFP_NET_CFG_RSS_HFUNC)
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+ * %NFP_NET_CFG_RSS_CAP_HFUNC: supported hash functions (same bits as
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+ * %NFP_NET_CFG_RSS_HFUNC)
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*/
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#define NFP_NET_CFG_RSS_CAP 0x0054
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#define NFP_NET_CFG_RSS_CAP_HFUNC 0xff000000
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/**
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* VXLAN/UDP encap configuration
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- * @NFP_NET_CFG_VXLAN_PORT: Base address of table of tunnels' UDP dst ports
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- * @NFP_NET_CFG_VXLAN_SZ: Size of the UDP port table in bytes
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+ * %NFP_NET_CFG_VXLAN_PORT: Base address of table of tunnels' UDP dst ports
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+ * %NFP_NET_CFG_VXLAN_SZ: Size of the UDP port table in bytes
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*/
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#define NFP_NET_CFG_VXLAN_PORT 0x0060
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#define NFP_NET_CFG_VXLAN_SZ 0x0008
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/**
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* BPF section
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- * @NFP_NET_CFG_BPF_ABI: BPF ABI version
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- * @NFP_NET_CFG_BPF_CAP: BPF capabilities
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- * @NFP_NET_CFG_BPF_MAX_LEN: Maximum size of JITed BPF code in bytes
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- * @NFP_NET_CFG_BPF_START: Offset at which BPF will be loaded
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- * @NFP_NET_CFG_BPF_DONE: Offset to jump to on exit
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- * @NFP_NET_CFG_BPF_STACK_SZ: Total size of stack area in 64B chunks
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- * @NFP_NET_CFG_BPF_INL_MTU: Packet data split offset in 64B chunks
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- * @NFP_NET_CFG_BPF_SIZE: Size of the JITed BPF code in instructions
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- * @NFP_NET_CFG_BPF_ADDR: DMA address of the buffer with JITed BPF code
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+ * %NFP_NET_CFG_BPF_ABI: BPF ABI version
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+ * %NFP_NET_CFG_BPF_CAP: BPF capabilities
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+ * %NFP_NET_CFG_BPF_MAX_LEN: Maximum size of JITed BPF code in bytes
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+ * %NFP_NET_CFG_BPF_START: Offset at which BPF will be loaded
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+ * %NFP_NET_CFG_BPF_DONE: Offset to jump to on exit
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+ * %NFP_NET_CFG_BPF_STACK_SZ: Total size of stack area in 64B chunks
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+ * %NFP_NET_CFG_BPF_INL_MTU: Packet data split offset in 64B chunks
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+ * %NFP_NET_CFG_BPF_SIZE: Size of the JITed BPF code in instructions
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+ * %NFP_NET_CFG_BPF_ADDR: DMA address of the buffer with JITed BPF code
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*/
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#define NFP_NET_CFG_BPF_ABI 0x0080
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#define NFP_NET_BPF_ABI 2
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@@ -278,9 +279,9 @@
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/**
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* RSS configuration (0x0100 - 0x01ac):
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* Used only when NFP_NET_CFG_CTRL_RSS is enabled
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- * @NFP_NET_CFG_RSS_CFG: RSS configuration word
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- * @NFP_NET_CFG_RSS_KEY: RSS "secret" key
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- * @NFP_NET_CFG_RSS_ITBL: RSS indirection table
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+ * %NFP_NET_CFG_RSS_CFG: RSS configuration word
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+ * %NFP_NET_CFG_RSS_KEY: RSS "secret" key
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+ * %NFP_NET_CFG_RSS_ITBL: RSS indirection table
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*/
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#define NFP_NET_CFG_RSS_BASE 0x0100
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#define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE
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@@ -305,13 +306,13 @@
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/**
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* TX ring configuration (0x200 - 0x800)
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- * @NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration
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- * @NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries)
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- * @NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries)
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- * @NFP_NET_CFG_TXR_SZ: Per TX ring ring size (1B entries)
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- * @NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries)
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- * @NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries)
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- * @NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation packet
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+ * %NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration
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+ * %NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries)
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+ * %NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries)
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+ * %NFP_NET_CFG_TXR_SZ: Per TX ring ring size (1B entries)
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+ * %NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries)
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+ * %NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries)
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+ * %NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation packet
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*/
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#define NFP_NET_CFG_TXR_BASE 0x0200
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#define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8))
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@@ -325,12 +326,12 @@
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/**
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* RX ring configuration (0x0800 - 0x0c00)
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- * @NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration
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- * @NFP_NET_CFG_RXR_ADDR: Per RX ring DMA address (8B entries)
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- * @NFP_NET_CFG_RXR_SZ: Per RX ring ring size (1B entries)
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- * @NFP_NET_CFG_RXR_VEC: Per RX ring MSI-X table entry (1B entries)
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- * @NFP_NET_CFG_RXR_PRIO: Per RX ring priority (1B entries)
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- * @NFP_NET_CFG_RXR_IRQ_MOD: Per RX ring interrupt moderation (4B entries)
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+ * %NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration
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+ * %NFP_NET_CFG_RXR_ADDR: Per RX ring DMA address (8B entries)
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+ * %NFP_NET_CFG_RXR_SZ: Per RX ring ring size (1B entries)
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+ * %NFP_NET_CFG_RXR_VEC: Per RX ring MSI-X table entry (1B entries)
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+ * %NFP_NET_CFG_RXR_PRIO: Per RX ring priority (1B entries)
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+ * %NFP_NET_CFG_RXR_IRQ_MOD: Per RX ring interrupt moderation (4B entries)
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*/
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#define NFP_NET_CFG_RXR_BASE 0x0800
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#define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8))
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@@ -343,7 +344,7 @@
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/**
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* Interrupt Control/Cause registers (0x0c00 - 0x0d00)
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* These registers are only used when MSI-X auto-masking is not
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- * enabled (@NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index
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+ * enabled (%NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index
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* by MSI-X entry and are 1B in size. If an entry is zero, the
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* corresponding entry is enabled. If the FW generates an interrupt,
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* it writes a cause into the corresponding field. This also masks
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@@ -393,8 +394,8 @@
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/**
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* Per ring stats (0x1000 - 0x1800)
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* options, 64bit per entry
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- * @NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count)
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- * @NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count)
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+ * %NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count)
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+ * %NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count)
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*/
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#define NFP_NET_CFG_TXR_STATS_BASE 0x1000
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#define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \
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@@ -418,10 +419,10 @@
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/**
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* VLAN filtering using general use mailbox
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- * @NFP_NET_CFG_VLAN_FILTER: Base address of VLAN filter mailbox
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- * @NFP_NET_CFG_VLAN_FILTER_VID: VLAN ID to filter
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- * @NFP_NET_CFG_VLAN_FILTER_PROTO: VLAN proto to filter
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- * @NFP_NET_CFG_VXLAN_SZ: Size of the VLAN filter mailbox in bytes
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+ * %NFP_NET_CFG_VLAN_FILTER: Base address of VLAN filter mailbox
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+ * %NFP_NET_CFG_VLAN_FILTER_VID: VLAN ID to filter
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+ * %NFP_NET_CFG_VLAN_FILTER_PROTO: VLAN proto to filter
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+ * %NFP_NET_CFG_VXLAN_SZ: Size of the VLAN filter mailbox in bytes
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*/
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#define NFP_NET_CFG_VLAN_FILTER NFP_NET_CFG_MBOX_VAL
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#define NFP_NET_CFG_VLAN_FILTER_VID NFP_NET_CFG_VLAN_FILTER
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