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@@ -43,7 +43,7 @@
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static inline bool fbc_supported(struct drm_i915_private *dev_priv)
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{
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- return dev_priv->fbc.activate != NULL;
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+ return HAS_FBC(dev_priv);
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}
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static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
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@@ -343,6 +343,38 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
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intel_fbc_recompress(dev_priv);
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}
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+static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
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+{
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+ if (INTEL_INFO(dev_priv)->gen >= 5)
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+ return ilk_fbc_is_active(dev_priv);
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+ else if (IS_GM45(dev_priv))
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+ return g4x_fbc_is_active(dev_priv);
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+ else
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+ return i8xx_fbc_is_active(dev_priv);
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+}
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+
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+static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
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+{
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+ if (INTEL_INFO(dev_priv)->gen >= 7)
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+ gen7_fbc_activate(dev_priv);
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+ else if (INTEL_INFO(dev_priv)->gen >= 5)
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+ ilk_fbc_activate(dev_priv);
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+ else if (IS_GM45(dev_priv))
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+ g4x_fbc_activate(dev_priv);
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+ else
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+ i8xx_fbc_activate(dev_priv);
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+}
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+
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+static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
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+{
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+ if (INTEL_INFO(dev_priv)->gen >= 5)
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+ ilk_fbc_deactivate(dev_priv);
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+ else if (IS_GM45(dev_priv))
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+ g4x_fbc_deactivate(dev_priv);
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+ else
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+ i8xx_fbc_deactivate(dev_priv);
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+}
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+
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/**
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* intel_fbc_is_active - Is FBC active?
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* @dev_priv: i915 device instance
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@@ -405,7 +437,7 @@ retry:
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goto retry;
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}
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- fbc->activate(dev_priv);
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+ intel_fbc_hw_activate(dev_priv);
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work->scheduled = false;
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@@ -451,7 +483,7 @@ static void intel_fbc_deactivate(struct drm_i915_private *dev_priv)
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fbc->work.scheduled = false;
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if (fbc->active)
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- fbc->deactivate(dev_priv);
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+ intel_fbc_hw_deactivate(dev_priv);
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}
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static bool multiple_pipes_ok(struct intel_crtc *crtc)
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@@ -713,7 +745,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc)
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/* FIXME: We lack the proper locking here, so only run this on the
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* platforms that need. */
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- if (dev_priv->fbc.activate == ilk_fbc_activate)
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+ if (INTEL_INFO(dev_priv)->gen >= 5 && INTEL_INFO(dev_priv)->gen < 7)
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cache->fb.ilk_ggtt_offset = i915_gem_obj_ggtt_offset(obj);
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cache->fb.pixel_format = fb->pixel_format;
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cache->fb.stride = fb->pitches[0];
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@@ -1223,30 +1255,13 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
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break;
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}
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- if (INTEL_INFO(dev_priv)->gen >= 7) {
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- fbc->is_active = ilk_fbc_is_active;
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- fbc->activate = gen7_fbc_activate;
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- fbc->deactivate = ilk_fbc_deactivate;
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- } else if (INTEL_INFO(dev_priv)->gen >= 5) {
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- fbc->is_active = ilk_fbc_is_active;
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- fbc->activate = ilk_fbc_activate;
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- fbc->deactivate = ilk_fbc_deactivate;
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- } else if (IS_GM45(dev_priv)) {
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- fbc->is_active = g4x_fbc_is_active;
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- fbc->activate = g4x_fbc_activate;
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- fbc->deactivate = g4x_fbc_deactivate;
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- } else {
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- fbc->is_active = i8xx_fbc_is_active;
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- fbc->activate = i8xx_fbc_activate;
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- fbc->deactivate = i8xx_fbc_deactivate;
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-
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- /* This value was pulled out of someone's hat */
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+ /* This value was pulled out of someone's hat */
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+ if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_GM45(dev_priv))
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I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
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- }
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/* We still don't have any sort of hardware state readout for FBC, so
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* deactivate it in case the BIOS activated it to make sure software
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* matches the hardware state. */
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- if (fbc->is_active(dev_priv))
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- fbc->deactivate(dev_priv);
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+ if (intel_fbc_hw_is_active(dev_priv))
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+ intel_fbc_hw_deactivate(dev_priv);
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}
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