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@@ -58,6 +58,186 @@
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#define GCC_QPIC_AHB_CLK 41
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#define GCC_QPIC_CLK 42
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#define PCNOC_BFDCD_CLK_SRC 43
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+#define GPLL2_MAIN 44
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+#define GPLL2 45
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+#define GPLL4_MAIN 46
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+#define GPLL4 47
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+#define GPLL6_MAIN 48
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+#define GPLL6 49
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+#define UBI32_PLL_MAIN 50
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+#define UBI32_PLL 51
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+#define NSS_CRYPTO_PLL_MAIN 52
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+#define NSS_CRYPTO_PLL 53
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+#define PCIE0_AXI_CLK_SRC 54
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+#define PCIE0_AUX_CLK_SRC 55
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+#define PCIE0_PIPE_CLK_SRC 56
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+#define PCIE1_AXI_CLK_SRC 57
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+#define PCIE1_AUX_CLK_SRC 58
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+#define PCIE1_PIPE_CLK_SRC 59
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+#define SDCC1_APPS_CLK_SRC 60
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+#define SDCC1_ICE_CORE_CLK_SRC 61
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+#define SDCC2_APPS_CLK_SRC 62
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+#define USB0_MASTER_CLK_SRC 63
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+#define USB0_AUX_CLK_SRC 64
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+#define USB0_MOCK_UTMI_CLK_SRC 65
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+#define USB0_PIPE_CLK_SRC 66
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+#define USB1_MASTER_CLK_SRC 67
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+#define USB1_AUX_CLK_SRC 68
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+#define USB1_MOCK_UTMI_CLK_SRC 69
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+#define USB1_PIPE_CLK_SRC 70
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+#define GCC_XO_CLK_SRC 71
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+#define SYSTEM_NOC_BFDCD_CLK_SRC 72
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+#define NSS_CE_CLK_SRC 73
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+#define NSS_NOC_BFDCD_CLK_SRC 74
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+#define NSS_CRYPTO_CLK_SRC 75
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+#define NSS_UBI0_CLK_SRC 76
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+#define NSS_UBI0_DIV_CLK_SRC 77
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+#define NSS_UBI1_CLK_SRC 78
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+#define NSS_UBI1_DIV_CLK_SRC 79
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+#define UBI_MPT_CLK_SRC 80
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+#define NSS_IMEM_CLK_SRC 81
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+#define NSS_PPE_CLK_SRC 82
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+#define NSS_PORT1_RX_CLK_SRC 83
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+#define NSS_PORT1_RX_DIV_CLK_SRC 84
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+#define NSS_PORT1_TX_CLK_SRC 85
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+#define NSS_PORT1_TX_DIV_CLK_SRC 86
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+#define NSS_PORT2_RX_CLK_SRC 87
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+#define NSS_PORT2_RX_DIV_CLK_SRC 88
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+#define NSS_PORT2_TX_CLK_SRC 89
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+#define NSS_PORT2_TX_DIV_CLK_SRC 90
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+#define NSS_PORT3_RX_CLK_SRC 91
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+#define NSS_PORT3_RX_DIV_CLK_SRC 92
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+#define NSS_PORT3_TX_CLK_SRC 93
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+#define NSS_PORT3_TX_DIV_CLK_SRC 94
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+#define NSS_PORT4_RX_CLK_SRC 95
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+#define NSS_PORT4_RX_DIV_CLK_SRC 96
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+#define NSS_PORT4_TX_CLK_SRC 97
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+#define NSS_PORT4_TX_DIV_CLK_SRC 98
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+#define NSS_PORT5_RX_CLK_SRC 99
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+#define NSS_PORT5_RX_DIV_CLK_SRC 100
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+#define NSS_PORT5_TX_CLK_SRC 101
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+#define NSS_PORT5_TX_DIV_CLK_SRC 102
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+#define NSS_PORT6_RX_CLK_SRC 103
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+#define NSS_PORT6_RX_DIV_CLK_SRC 104
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+#define NSS_PORT6_TX_CLK_SRC 105
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+#define NSS_PORT6_TX_DIV_CLK_SRC 106
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+#define CRYPTO_CLK_SRC 107
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+#define GP1_CLK_SRC 108
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+#define GP2_CLK_SRC 109
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+#define GP3_CLK_SRC 110
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+#define GCC_PCIE0_AHB_CLK 111
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+#define GCC_PCIE0_AUX_CLK 112
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+#define GCC_PCIE0_AXI_M_CLK 113
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+#define GCC_PCIE0_AXI_S_CLK 114
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+#define GCC_PCIE0_PIPE_CLK 115
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+#define GCC_SYS_NOC_PCIE0_AXI_CLK 116
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+#define GCC_PCIE1_AHB_CLK 117
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+#define GCC_PCIE1_AUX_CLK 118
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+#define GCC_PCIE1_AXI_M_CLK 119
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+#define GCC_PCIE1_AXI_S_CLK 120
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+#define GCC_PCIE1_PIPE_CLK 121
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+#define GCC_SYS_NOC_PCIE1_AXI_CLK 122
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+#define GCC_USB0_AUX_CLK 123
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+#define GCC_SYS_NOC_USB0_AXI_CLK 124
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+#define GCC_USB0_MASTER_CLK 125
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+#define GCC_USB0_MOCK_UTMI_CLK 126
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+#define GCC_USB0_PHY_CFG_AHB_CLK 127
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+#define GCC_USB0_PIPE_CLK 128
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+#define GCC_USB0_SLEEP_CLK 129
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+#define GCC_USB1_AUX_CLK 130
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+#define GCC_SYS_NOC_USB1_AXI_CLK 131
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+#define GCC_USB1_MASTER_CLK 132
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+#define GCC_USB1_MOCK_UTMI_CLK 133
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+#define GCC_USB1_PHY_CFG_AHB_CLK 134
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+#define GCC_USB1_PIPE_CLK 135
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+#define GCC_USB1_SLEEP_CLK 136
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+#define GCC_SDCC1_AHB_CLK 137
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+#define GCC_SDCC1_APPS_CLK 138
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+#define GCC_SDCC1_ICE_CORE_CLK 139
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+#define GCC_SDCC2_AHB_CLK 140
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+#define GCC_SDCC2_APPS_CLK 141
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+#define GCC_MEM_NOC_NSS_AXI_CLK 142
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+#define GCC_NSS_CE_APB_CLK 143
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+#define GCC_NSS_CE_AXI_CLK 144
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+#define GCC_NSS_CFG_CLK 145
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+#define GCC_NSS_CRYPTO_CLK 146
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+#define GCC_NSS_CSR_CLK 147
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+#define GCC_NSS_EDMA_CFG_CLK 148
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+#define GCC_NSS_EDMA_CLK 149
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+#define GCC_NSS_IMEM_CLK 150
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+#define GCC_NSS_NOC_CLK 151
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+#define GCC_NSS_PPE_BTQ_CLK 152
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+#define GCC_NSS_PPE_CFG_CLK 153
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+#define GCC_NSS_PPE_CLK 154
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+#define GCC_NSS_PPE_IPE_CLK 155
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+#define GCC_NSS_PTP_REF_CLK 156
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+#define GCC_NSSNOC_CE_APB_CLK 157
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+#define GCC_NSSNOC_CE_AXI_CLK 158
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+#define GCC_NSSNOC_CRYPTO_CLK 159
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+#define GCC_NSSNOC_PPE_CFG_CLK 160
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+#define GCC_NSSNOC_PPE_CLK 161
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+#define GCC_NSSNOC_QOSGEN_REF_CLK 162
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+#define GCC_NSSNOC_SNOC_CLK 163
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+#define GCC_NSSNOC_TIMEOUT_REF_CLK 164
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+#define GCC_NSSNOC_UBI0_AHB_CLK 165
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+#define GCC_NSSNOC_UBI1_AHB_CLK 166
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+#define GCC_UBI0_AHB_CLK 167
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+#define GCC_UBI0_AXI_CLK 168
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+#define GCC_UBI0_NC_AXI_CLK 169
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+#define GCC_UBI0_CORE_CLK 170
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+#define GCC_UBI0_MPT_CLK 171
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+#define GCC_UBI1_AHB_CLK 172
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+#define GCC_UBI1_AXI_CLK 173
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+#define GCC_UBI1_NC_AXI_CLK 174
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+#define GCC_UBI1_CORE_CLK 175
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+#define GCC_UBI1_MPT_CLK 176
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+#define GCC_CMN_12GPLL_AHB_CLK 177
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+#define GCC_CMN_12GPLL_SYS_CLK 178
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+#define GCC_MDIO_AHB_CLK 179
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+#define GCC_UNIPHY0_AHB_CLK 180
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+#define GCC_UNIPHY0_SYS_CLK 181
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+#define GCC_UNIPHY1_AHB_CLK 182
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+#define GCC_UNIPHY1_SYS_CLK 183
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+#define GCC_UNIPHY2_AHB_CLK 184
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+#define GCC_UNIPHY2_SYS_CLK 185
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+#define GCC_NSS_PORT1_RX_CLK 186
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+#define GCC_NSS_PORT1_TX_CLK 187
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+#define GCC_NSS_PORT2_RX_CLK 188
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+#define GCC_NSS_PORT2_TX_CLK 189
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+#define GCC_NSS_PORT3_RX_CLK 190
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+#define GCC_NSS_PORT3_TX_CLK 191
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+#define GCC_NSS_PORT4_RX_CLK 192
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+#define GCC_NSS_PORT4_TX_CLK 193
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+#define GCC_NSS_PORT5_RX_CLK 194
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+#define GCC_NSS_PORT5_TX_CLK 195
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+#define GCC_NSS_PORT6_RX_CLK 196
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+#define GCC_NSS_PORT6_TX_CLK 197
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+#define GCC_PORT1_MAC_CLK 198
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+#define GCC_PORT2_MAC_CLK 199
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+#define GCC_PORT3_MAC_CLK 200
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+#define GCC_PORT4_MAC_CLK 201
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+#define GCC_PORT5_MAC_CLK 202
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+#define GCC_PORT6_MAC_CLK 203
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+#define GCC_UNIPHY0_PORT1_RX_CLK 204
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+#define GCC_UNIPHY0_PORT1_TX_CLK 205
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+#define GCC_UNIPHY0_PORT2_RX_CLK 206
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+#define GCC_UNIPHY0_PORT2_TX_CLK 207
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+#define GCC_UNIPHY0_PORT3_RX_CLK 208
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+#define GCC_UNIPHY0_PORT3_TX_CLK 209
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+#define GCC_UNIPHY0_PORT4_RX_CLK 210
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+#define GCC_UNIPHY0_PORT4_TX_CLK 211
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+#define GCC_UNIPHY0_PORT5_RX_CLK 212
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+#define GCC_UNIPHY0_PORT5_TX_CLK 213
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+#define GCC_UNIPHY1_PORT5_RX_CLK 214
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+#define GCC_UNIPHY1_PORT5_TX_CLK 215
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+#define GCC_UNIPHY2_PORT6_RX_CLK 216
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+#define GCC_UNIPHY2_PORT6_TX_CLK 217
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+#define GCC_CRYPTO_AHB_CLK 218
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+#define GCC_CRYPTO_AXI_CLK 219
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+#define GCC_CRYPTO_CLK 220
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+#define GCC_GP1_CLK 221
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+#define GCC_GP2_CLK 222
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+#define GCC_GP3_CLK 223
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#define GCC_BLSP1_BCR 0
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#define GCC_BLSP1_QUP1_BCR 1
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Abhishek Sahu