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@@ -109,27 +109,13 @@ static const struct regmap_config crystal_cove_regmap_config = {
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};
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static const struct regmap_irq crystal_cove_irqs[] = {
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- [CRYSTAL_COVE_IRQ_PWRSRC] = {
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- .mask = BIT(CRYSTAL_COVE_IRQ_PWRSRC),
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- },
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- [CRYSTAL_COVE_IRQ_THRM] = {
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- .mask = BIT(CRYSTAL_COVE_IRQ_THRM),
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- },
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- [CRYSTAL_COVE_IRQ_BCU] = {
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- .mask = BIT(CRYSTAL_COVE_IRQ_BCU),
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- },
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- [CRYSTAL_COVE_IRQ_ADC] = {
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- .mask = BIT(CRYSTAL_COVE_IRQ_ADC),
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- },
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- [CRYSTAL_COVE_IRQ_CHGR] = {
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- .mask = BIT(CRYSTAL_COVE_IRQ_CHGR),
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- },
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- [CRYSTAL_COVE_IRQ_GPIO] = {
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- .mask = BIT(CRYSTAL_COVE_IRQ_GPIO),
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- },
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- [CRYSTAL_COVE_IRQ_VHDMIOCP] = {
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- .mask = BIT(CRYSTAL_COVE_IRQ_VHDMIOCP),
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- },
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+ REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_PWRSRC, 0, BIT(CRYSTAL_COVE_IRQ_PWRSRC)),
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+ REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_THRM, 0, BIT(CRYSTAL_COVE_IRQ_THRM)),
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+ REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_BCU, 0, BIT(CRYSTAL_COVE_IRQ_BCU)),
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+ REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_ADC, 0, BIT(CRYSTAL_COVE_IRQ_ADC)),
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+ REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_CHGR, 0, BIT(CRYSTAL_COVE_IRQ_CHGR)),
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+ REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_GPIO, 0, BIT(CRYSTAL_COVE_IRQ_GPIO)),
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+ REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_VHDMIOCP, 0, BIT(CRYSTAL_COVE_IRQ_VHDMIOCP)),
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};
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static const struct regmap_irq_chip crystal_cove_irq_chip = {
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