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@@ -1370,6 +1370,20 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
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std r6, VCPU_ACOP(r9)
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stw r7, VCPU_GUEST_PID(r9)
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std r8, VCPU_WORT(r9)
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+ /*
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+ * Restore various registers to 0, where non-zero values
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+ * set by the guest could disrupt the host.
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+ */
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+ li r0, 0
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+ mtspr SPRN_IAMR, r0
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+ mtspr SPRN_CIABR, r0
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+ mtspr SPRN_DAWRX, r0
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+ mtspr SPRN_TCSCR, r0
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+ mtspr SPRN_WORT, r0
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+ /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
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+ li r0, 1
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+ sldi r0, r0, 31
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+ mtspr SPRN_MMCRS, r0
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8:
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/* Save and reset AMR and UAMOR before turning on the MMU */
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Paolo Bonzini