|
@@ -165,7 +165,6 @@ static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
|
|
|
static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
|
|
|
{
|
|
|
struct device_node *np = hdmi->dev->of_node;
|
|
|
- int ret;
|
|
|
|
|
|
hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
|
|
|
if (IS_ERR(hdmi->regmap)) {
|
|
@@ -193,13 +192,6 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
|
|
|
return PTR_ERR(hdmi->grf_clk);
|
|
|
}
|
|
|
|
|
|
- ret = clk_prepare_enable(hdmi->vpll_clk);
|
|
|
- if (ret) {
|
|
|
- DRM_DEV_ERROR(hdmi->dev,
|
|
|
- "Failed to enable HDMI vpll: %d\n", ret);
|
|
|
- return ret;
|
|
|
- }
|
|
|
-
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
@@ -374,6 +366,13 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
+ ret = clk_prepare_enable(hdmi->vpll_clk);
|
|
|
+ if (ret) {
|
|
|
+ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
|
|
|
+ ret);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
|
|
|
drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
|
|
|
DRM_MODE_ENCODER_TMDS, NULL);
|
|
@@ -389,6 +388,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
|
|
|
if (IS_ERR(hdmi->hdmi)) {
|
|
|
ret = PTR_ERR(hdmi->hdmi);
|
|
|
drm_encoder_cleanup(encoder);
|
|
|
+ clk_disable_unprepare(hdmi->vpll_clk);
|
|
|
}
|
|
|
|
|
|
return ret;
|
|
@@ -400,6 +400,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
|
|
|
struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
|
|
|
|
|
|
dw_hdmi_unbind(hdmi->hdmi);
|
|
|
+ clk_disable_unprepare(hdmi->vpll_clk);
|
|
|
}
|
|
|
|
|
|
static const struct component_ops dw_hdmi_rockchip_ops = {
|