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@@ -353,6 +353,34 @@ static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw)
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PARENTS(clk_pxa27x_memory) = { "osc_13mhz", "system_bus", "run" };
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PARENTS(clk_pxa27x_memory) = { "osc_13mhz", "system_bus", "run" };
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MUX_RO_RATE_RO_OPS(clk_pxa27x_memory, "memory");
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MUX_RO_RATE_RO_OPS(clk_pxa27x_memory, "memory");
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+#define DUMMY_CLK(_con_id, _dev_id, _parent) \
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+ { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
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+struct dummy_clk {
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+ const char *con_id;
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+ const char *dev_id;
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+ const char *parent;
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+};
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+static struct dummy_clk dummy_clks[] __initdata = {
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+ DUMMY_CLK(NULL, "pxa27x-gpio", "osc_32_768khz"),
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+ DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
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+ DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
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+};
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+
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+static void __init pxa27x_dummy_clocks_init(void)
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+{
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+ struct clk *clk;
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+ struct dummy_clk *d;
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+ const char *name;
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
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+ d = &dummy_clks[i];
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+ name = d->dev_id ? d->dev_id : d->con_id;
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+ clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
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+ clk_register_clkdev(clk, d->con_id, d->dev_id);
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+ }
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+}
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+
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static void __init pxa27x_base_clocks_init(void)
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static void __init pxa27x_base_clocks_init(void)
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{
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{
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pxa27x_register_plls();
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pxa27x_register_plls();
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@@ -365,6 +393,7 @@ static void __init pxa27x_base_clocks_init(void)
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int __init pxa27x_clocks_init(void)
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int __init pxa27x_clocks_init(void)
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{
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{
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pxa27x_base_clocks_init();
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pxa27x_base_clocks_init();
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+ pxa27x_dummy_clocks_init();
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return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks));
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return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks));
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}
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}
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