|
@@ -589,6 +589,28 @@
|
|
/* EntryHI bit definition */
|
|
/* EntryHI bit definition */
|
|
#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
|
|
#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
|
|
|
|
|
|
|
|
+/* R3000 EntryLo bit definitions */
|
|
|
|
+#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
|
|
|
|
+#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
|
|
|
|
+#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
|
|
|
|
+#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
|
|
|
|
+
|
|
|
|
+/* R4000 compatible EntryLo bit definitions */
|
|
|
|
+#define MIPS_ENTRYLO_G (_ULCAST_(1) << 0)
|
|
|
|
+#define MIPS_ENTRYLO_V (_ULCAST_(1) << 1)
|
|
|
|
+#define MIPS_ENTRYLO_D (_ULCAST_(1) << 2)
|
|
|
|
+#define MIPS_ENTRYLO_C_SHIFT 3
|
|
|
|
+#define MIPS_ENTRYLO_C (_ULCAST_(7) << MIPS_ENTRYLO_C_SHIFT)
|
|
|
|
+#ifdef CONFIG_64BIT
|
|
|
|
+/* as read by dmfc0 */
|
|
|
|
+#define MIPS_ENTRYLO_XI (_ULCAST_(1) << 62)
|
|
|
|
+#define MIPS_ENTRYLO_RI (_ULCAST_(1) << 63)
|
|
|
|
+#else
|
|
|
|
+/* as read by mfc0 */
|
|
|
|
+#define MIPS_ENTRYLO_XI (_ULCAST_(1) << 30)
|
|
|
|
+#define MIPS_ENTRYLO_RI (_ULCAST_(1) << 31)
|
|
|
|
+#endif
|
|
|
|
+
|
|
/* CMGCRBase bit definitions */
|
|
/* CMGCRBase bit definitions */
|
|
#define MIPS_CMGCRB_BASE 11
|
|
#define MIPS_CMGCRB_BASE 11
|
|
#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
|
|
#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
|