|
@@ -16,9 +16,9 @@
|
|
|
|
|
|
|
|
#include <linux/io.h>
|
|
#include <linux/io.h>
|
|
|
#include <asm/unaligned.h>
|
|
#include <asm/unaligned.h>
|
|
|
-#include <linux/pci.h>
|
|
|
|
|
|
|
|
|
|
-#include "ath9k.h"
|
|
|
|
|
|
|
+#include "hw.h"
|
|
|
|
|
+#include "rc.h"
|
|
|
#include "initvals.h"
|
|
#include "initvals.h"
|
|
|
|
|
|
|
|
#define ATH9K_CLOCK_RATE_CCK 22
|
|
#define ATH9K_CLOCK_RATE_CCK 22
|
|
@@ -26,21 +26,37 @@
|
|
|
#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
|
|
#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
|
|
|
|
|
|
|
|
static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
|
|
static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
|
|
|
-static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
|
|
|
|
|
- enum ath9k_ht_macmode macmode);
|
|
|
|
|
|
|
+static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
|
|
|
static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
|
|
static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
|
|
|
struct ar5416_eeprom_def *pEepData,
|
|
struct ar5416_eeprom_def *pEepData,
|
|
|
u32 reg, u32 value);
|
|
u32 reg, u32 value);
|
|
|
static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
|
|
static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
|
|
|
static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
|
|
static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
|
|
|
|
|
|
|
|
|
|
+MODULE_AUTHOR("Atheros Communications");
|
|
|
|
|
+MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
|
|
|
|
|
+MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
|
|
|
|
|
+MODULE_LICENSE("Dual BSD/GPL");
|
|
|
|
|
+
|
|
|
|
|
+static int __init ath9k_init(void)
|
|
|
|
|
+{
|
|
|
|
|
+ return 0;
|
|
|
|
|
+}
|
|
|
|
|
+module_init(ath9k_init);
|
|
|
|
|
+
|
|
|
|
|
+static void __exit ath9k_exit(void)
|
|
|
|
|
+{
|
|
|
|
|
+ return;
|
|
|
|
|
+}
|
|
|
|
|
+module_exit(ath9k_exit);
|
|
|
|
|
+
|
|
|
/********************/
|
|
/********************/
|
|
|
/* Helper Functions */
|
|
/* Helper Functions */
|
|
|
/********************/
|
|
/********************/
|
|
|
|
|
|
|
|
static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
|
|
static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
|
|
|
{
|
|
{
|
|
|
- struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
|
|
|
|
|
|
|
+ struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
|
|
|
|
|
|
|
|
if (!ah->curchan) /* should really check for CCK instead */
|
|
if (!ah->curchan) /* should really check for CCK instead */
|
|
|
return clks / ATH9K_CLOCK_RATE_CCK;
|
|
return clks / ATH9K_CLOCK_RATE_CCK;
|
|
@@ -52,7 +68,7 @@ static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
|
|
|
|
|
|
|
|
static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
|
|
static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
|
|
|
{
|
|
{
|
|
|
- struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
|
|
|
|
|
|
|
+ struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
|
|
|
|
|
|
|
|
if (conf_is_ht40(conf))
|
|
if (conf_is_ht40(conf))
|
|
|
return ath9k_hw_mac_usec(ah, clks) / 2;
|
|
return ath9k_hw_mac_usec(ah, clks) / 2;
|
|
@@ -62,7 +78,7 @@ static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
|
|
|
|
|
|
|
|
static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
|
|
static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
|
|
|
{
|
|
{
|
|
|
- struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
|
|
|
|
|
|
|
+ struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
|
|
|
|
|
|
|
|
if (!ah->curchan) /* should really check for CCK instead */
|
|
if (!ah->curchan) /* should really check for CCK instead */
|
|
|
return usecs *ATH9K_CLOCK_RATE_CCK;
|
|
return usecs *ATH9K_CLOCK_RATE_CCK;
|
|
@@ -73,7 +89,7 @@ static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
|
|
|
|
|
|
|
|
static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
|
|
static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
|
|
|
{
|
|
{
|
|
|
- struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
|
|
|
|
|
|
|
+ struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
|
|
|
|
|
|
|
|
if (conf_is_ht40(conf))
|
|
if (conf_is_ht40(conf))
|
|
|
return ath9k_hw_mac_clks(ah, usecs) * 2;
|
|
return ath9k_hw_mac_clks(ah, usecs) * 2;
|
|
@@ -81,38 +97,6 @@ static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
|
|
|
return ath9k_hw_mac_clks(ah, usecs);
|
|
return ath9k_hw_mac_clks(ah, usecs);
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
-/*
|
|
|
|
|
- * Read and write, they both share the same lock. We do this to serialize
|
|
|
|
|
- * reads and writes on Atheros 802.11n PCI devices only. This is required
|
|
|
|
|
- * as the FIFO on these devices can only accept sanely 2 requests. After
|
|
|
|
|
- * that the device goes bananas. Serializing the reads/writes prevents this
|
|
|
|
|
- * from happening.
|
|
|
|
|
- */
|
|
|
|
|
-
|
|
|
|
|
-void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
|
|
|
|
|
-{
|
|
|
|
|
- if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
|
|
|
|
|
- unsigned long flags;
|
|
|
|
|
- spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
|
|
|
|
|
- iowrite32(val, ah->ah_sc->mem + reg_offset);
|
|
|
|
|
- spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
|
|
|
|
|
- } else
|
|
|
|
|
- iowrite32(val, ah->ah_sc->mem + reg_offset);
|
|
|
|
|
-}
|
|
|
|
|
-
|
|
|
|
|
-unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
|
|
|
|
|
-{
|
|
|
|
|
- u32 val;
|
|
|
|
|
- if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
|
|
|
|
|
- unsigned long flags;
|
|
|
|
|
- spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
|
|
|
|
|
- val = ioread32(ah->ah_sc->mem + reg_offset);
|
|
|
|
|
- spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
|
|
|
|
|
- } else
|
|
|
|
|
- val = ioread32(ah->ah_sc->mem + reg_offset);
|
|
|
|
|
- return val;
|
|
|
|
|
-}
|
|
|
|
|
-
|
|
|
|
|
bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
|
|
bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
|
|
|
{
|
|
{
|
|
|
int i;
|
|
int i;
|
|
@@ -126,12 +110,13 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
|
|
|
udelay(AH_TIME_QUANTUM);
|
|
udelay(AH_TIME_QUANTUM);
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_ANY,
|
|
|
|
|
- "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
|
|
|
|
|
- timeout, reg, REG_READ(ah, reg), mask, val);
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
|
|
|
|
|
+ "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
|
|
|
|
|
+ timeout, reg, REG_READ(ah, reg), mask, val);
|
|
|
|
|
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_wait);
|
|
|
|
|
|
|
|
u32 ath9k_hw_reverse_bits(u32 val, u32 n)
|
|
u32 ath9k_hw_reverse_bits(u32 val, u32 n)
|
|
|
{
|
|
{
|
|
@@ -210,15 +195,16 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah,
|
|
|
}
|
|
}
|
|
|
break;
|
|
break;
|
|
|
default:
|
|
default:
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
|
|
|
|
- "Unknown phy %u (rate ix %u)\n",
|
|
|
|
|
- rates->info[rateix].phy, rateix);
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
|
|
|
|
|
+ "Unknown phy %u (rate ix %u)\n",
|
|
|
|
|
+ rates->info[rateix].phy, rateix);
|
|
|
txTime = 0;
|
|
txTime = 0;
|
|
|
break;
|
|
break;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
return txTime;
|
|
return txTime;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_computetxtime);
|
|
|
|
|
|
|
|
void ath9k_hw_get_channel_centers(struct ath_hw *ah,
|
|
void ath9k_hw_get_channel_centers(struct ath_hw *ah,
|
|
|
struct ath9k_channel *chan,
|
|
struct ath9k_channel *chan,
|
|
@@ -245,10 +231,9 @@ void ath9k_hw_get_channel_centers(struct ath_hw *ah,
|
|
|
|
|
|
|
|
centers->ctl_center =
|
|
centers->ctl_center =
|
|
|
centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
|
|
centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
|
|
|
|
|
+ /* 25 MHz spacing is supported by hw but not on upper layers */
|
|
|
centers->ext_center =
|
|
centers->ext_center =
|
|
|
- centers->synth_center + (extoff *
|
|
|
|
|
- ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
|
|
|
|
|
- HT40_CHANNEL_CENTER_SHIFT : 15));
|
|
|
|
|
|
|
+ centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
/******************/
|
|
/******************/
|
|
@@ -317,6 +302,7 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
|
|
|
|
|
|
|
|
static bool ath9k_hw_chip_test(struct ath_hw *ah)
|
|
static bool ath9k_hw_chip_test(struct ath_hw *ah)
|
|
|
{
|
|
{
|
|
|
|
|
+ struct ath_common *common = ath9k_hw_common(ah);
|
|
|
u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
|
|
u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
|
|
|
u32 regHold[2];
|
|
u32 regHold[2];
|
|
|
u32 patternData[4] = { 0x55555555,
|
|
u32 patternData[4] = { 0x55555555,
|
|
@@ -335,10 +321,11 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
|
|
|
REG_WRITE(ah, addr, wrData);
|
|
REG_WRITE(ah, addr, wrData);
|
|
|
rdData = REG_READ(ah, addr);
|
|
rdData = REG_READ(ah, addr);
|
|
|
if (rdData != wrData) {
|
|
if (rdData != wrData) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
|
|
|
|
- "address test failed "
|
|
|
|
|
- "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
|
|
|
|
|
- addr, wrData, rdData);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_FATAL,
|
|
|
|
|
+ "address test failed "
|
|
|
|
|
+ "addr: 0x%08x - wr:0x%08x != "
|
|
|
|
|
+ "rd:0x%08x\n",
|
|
|
|
|
+ addr, wrData, rdData);
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
@@ -347,10 +334,11 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
|
|
|
REG_WRITE(ah, addr, wrData);
|
|
REG_WRITE(ah, addr, wrData);
|
|
|
rdData = REG_READ(ah, addr);
|
|
rdData = REG_READ(ah, addr);
|
|
|
if (wrData != rdData) {
|
|
if (wrData != rdData) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
|
|
|
|
- "address test failed "
|
|
|
|
|
- "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
|
|
|
|
|
- addr, wrData, rdData);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_FATAL,
|
|
|
|
|
+ "address test failed "
|
|
|
|
|
+ "addr: 0x%08x - wr:0x%08x != "
|
|
|
|
|
+ "rd:0x%08x\n",
|
|
|
|
|
+ addr, wrData, rdData);
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
@@ -433,6 +421,7 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
|
|
|
if (num_possible_cpus() > 1)
|
|
if (num_possible_cpus() > 1)
|
|
|
ah->config.serialize_regmode = SER_REG_MODE_AUTO;
|
|
ah->config.serialize_regmode = SER_REG_MODE_AUTO;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_init);
|
|
|
|
|
|
|
|
static void ath9k_hw_init_defaults(struct ath_hw *ah)
|
|
static void ath9k_hw_init_defaults(struct ath_hw *ah)
|
|
|
{
|
|
{
|
|
@@ -472,8 +461,8 @@ static int ath9k_hw_rfattach(struct ath_hw *ah)
|
|
|
|
|
|
|
|
rfStatus = ath9k_hw_init_rf(ah, &ecode);
|
|
rfStatus = ath9k_hw_init_rf(ah, &ecode);
|
|
|
if (!rfStatus) {
|
|
if (!rfStatus) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
|
|
|
|
- "RF setup failed, status: %u\n", ecode);
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
|
|
|
|
|
+ "RF setup failed, status: %u\n", ecode);
|
|
|
return ecode;
|
|
return ecode;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
@@ -497,9 +486,9 @@ static int ath9k_hw_rf_claim(struct ath_hw *ah)
|
|
|
case AR_RAD2122_SREV_MAJOR:
|
|
case AR_RAD2122_SREV_MAJOR:
|
|
|
break;
|
|
break;
|
|
|
default:
|
|
default:
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
|
|
|
|
- "Radio Chip Rev 0x%02X not supported\n",
|
|
|
|
|
- val & AR_RADIO_SREV_MAJOR);
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
|
|
|
|
|
+ "Radio Chip Rev 0x%02X not supported\n",
|
|
|
|
|
+ val & AR_RADIO_SREV_MAJOR);
|
|
|
return -EOPNOTSUPP;
|
|
return -EOPNOTSUPP;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
@@ -510,6 +499,7 @@ static int ath9k_hw_rf_claim(struct ath_hw *ah)
|
|
|
|
|
|
|
|
static int ath9k_hw_init_macaddr(struct ath_hw *ah)
|
|
static int ath9k_hw_init_macaddr(struct ath_hw *ah)
|
|
|
{
|
|
{
|
|
|
|
|
+ struct ath_common *common = ath9k_hw_common(ah);
|
|
|
u32 sum;
|
|
u32 sum;
|
|
|
int i;
|
|
int i;
|
|
|
u16 eeval;
|
|
u16 eeval;
|
|
@@ -518,8 +508,8 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
|
|
|
for (i = 0; i < 3; i++) {
|
|
for (i = 0; i < 3; i++) {
|
|
|
eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
|
|
eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
|
|
|
sum += eeval;
|
|
sum += eeval;
|
|
|
- ah->macaddr[2 * i] = eeval >> 8;
|
|
|
|
|
- ah->macaddr[2 * i + 1] = eeval & 0xff;
|
|
|
|
|
|
|
+ common->macaddr[2 * i] = eeval >> 8;
|
|
|
|
|
+ common->macaddr[2 * i + 1] = eeval & 0xff;
|
|
|
}
|
|
}
|
|
|
if (sum == 0 || sum == 0xffff * 3)
|
|
if (sum == 0 || sum == 0xffff * 3)
|
|
|
return -EADDRNOTAVAIL;
|
|
return -EADDRNOTAVAIL;
|
|
@@ -590,8 +580,10 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
|
|
|
if (ecode != 0)
|
|
if (ecode != 0)
|
|
|
return ecode;
|
|
return ecode;
|
|
|
|
|
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
|
|
|
|
|
- ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
|
|
|
|
|
+ "Eeprom VER: %d, REV: %d\n",
|
|
|
|
|
+ ah->eep_ops->get_eeprom_ver(ah),
|
|
|
|
|
+ ah->eep_ops->get_eeprom_rev(ah));
|
|
|
|
|
|
|
|
ecode = ath9k_hw_rfattach(ah);
|
|
ecode = ath9k_hw_rfattach(ah);
|
|
|
if (ecode != 0)
|
|
if (ecode != 0)
|
|
@@ -617,6 +609,7 @@ static bool ath9k_hw_devid_supported(u16 devid)
|
|
|
case AR9285_DEVID_PCIE:
|
|
case AR9285_DEVID_PCIE:
|
|
|
case AR5416_DEVID_AR9287_PCI:
|
|
case AR5416_DEVID_AR9287_PCI:
|
|
|
case AR5416_DEVID_AR9287_PCIE:
|
|
case AR5416_DEVID_AR9287_PCIE:
|
|
|
|
|
+ case AR9271_USB:
|
|
|
return true;
|
|
return true;
|
|
|
default:
|
|
default:
|
|
|
break;
|
|
break;
|
|
@@ -634,9 +627,8 @@ static bool ath9k_hw_macversion_supported(u32 macversion)
|
|
|
case AR_SREV_VERSION_9280:
|
|
case AR_SREV_VERSION_9280:
|
|
|
case AR_SREV_VERSION_9285:
|
|
case AR_SREV_VERSION_9285:
|
|
|
case AR_SREV_VERSION_9287:
|
|
case AR_SREV_VERSION_9287:
|
|
|
- return true;
|
|
|
|
|
- /* Not yet */
|
|
|
|
|
case AR_SREV_VERSION_9271:
|
|
case AR_SREV_VERSION_9271:
|
|
|
|
|
+ return true;
|
|
|
default:
|
|
default:
|
|
|
break;
|
|
break;
|
|
|
}
|
|
}
|
|
@@ -905,21 +897,27 @@ static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
|
|
|
|
|
|
|
|
int ath9k_hw_init(struct ath_hw *ah)
|
|
int ath9k_hw_init(struct ath_hw *ah)
|
|
|
{
|
|
{
|
|
|
|
|
+ struct ath_common *common = ath9k_hw_common(ah);
|
|
|
int r = 0;
|
|
int r = 0;
|
|
|
|
|
|
|
|
- if (!ath9k_hw_devid_supported(ah->hw_version.devid))
|
|
|
|
|
|
|
+ if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
|
|
|
|
|
+ ath_print(common, ATH_DBG_FATAL,
|
|
|
|
|
+ "Unsupported device ID: 0x%0x\n",
|
|
|
|
|
+ ah->hw_version.devid);
|
|
|
return -EOPNOTSUPP;
|
|
return -EOPNOTSUPP;
|
|
|
|
|
+ }
|
|
|
|
|
|
|
|
ath9k_hw_init_defaults(ah);
|
|
ath9k_hw_init_defaults(ah);
|
|
|
ath9k_hw_init_config(ah);
|
|
ath9k_hw_init_config(ah);
|
|
|
|
|
|
|
|
if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
|
|
if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_FATAL,
|
|
|
|
|
+ "Couldn't reset chip\n");
|
|
|
return -EIO;
|
|
return -EIO;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
|
|
if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
|
|
|
return -EIO;
|
|
return -EIO;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
@@ -934,14 +932,14 @@ int ath9k_hw_init(struct ath_hw *ah)
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
|
|
|
ah->config.serialize_regmode);
|
|
ah->config.serialize_regmode);
|
|
|
|
|
|
|
|
if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
|
|
if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
|
|
|
|
- "Mac Chip Rev 0x%02x.%x is not supported by "
|
|
|
|
|
- "this driver\n", ah->hw_version.macVersion,
|
|
|
|
|
- ah->hw_version.macRev);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_FATAL,
|
|
|
|
|
+ "Mac Chip Rev 0x%02x.%x is not supported by "
|
|
|
|
|
+ "this driver\n", ah->hw_version.macVersion,
|
|
|
|
|
+ ah->hw_version.macRev);
|
|
|
return -EOPNOTSUPP;
|
|
return -EOPNOTSUPP;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
@@ -969,6 +967,16 @@ int ath9k_hw_init(struct ath_hw *ah)
|
|
|
else
|
|
else
|
|
|
ath9k_hw_disablepcie(ah);
|
|
ath9k_hw_disablepcie(ah);
|
|
|
|
|
|
|
|
|
|
+ /* Support for Japan ch.14 (2484) spread */
|
|
|
|
|
+ if (AR_SREV_9287_11_OR_LATER(ah)) {
|
|
|
|
|
+ INIT_INI_ARRAY(&ah->iniCckfirNormal,
|
|
|
|
|
+ ar9287Common_normal_cck_fir_coeff_92871_1,
|
|
|
|
|
+ ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
|
|
|
|
|
+ INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
|
|
|
|
|
+ ar9287Common_japan_2484_cck_fir_coeff_92871_1,
|
|
|
|
|
+ ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
r = ath9k_hw_post_init(ah);
|
|
r = ath9k_hw_post_init(ah);
|
|
|
if (r)
|
|
if (r)
|
|
|
return r;
|
|
return r;
|
|
@@ -979,8 +987,8 @@ int ath9k_hw_init(struct ath_hw *ah)
|
|
|
|
|
|
|
|
r = ath9k_hw_init_macaddr(ah);
|
|
r = ath9k_hw_init_macaddr(ah);
|
|
|
if (r) {
|
|
if (r) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
|
|
|
|
- "Failed to initialize MAC address\n");
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_FATAL,
|
|
|
|
|
+ "Failed to initialize MAC address\n");
|
|
|
return r;
|
|
return r;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
@@ -991,6 +999,8 @@ int ath9k_hw_init(struct ath_hw *ah)
|
|
|
|
|
|
|
|
ath9k_init_nfcal_hist_buffer(ah);
|
|
ath9k_init_nfcal_hist_buffer(ah);
|
|
|
|
|
|
|
|
|
|
+ common->state = ATH_HW_INITIALIZED;
|
|
|
|
|
+
|
|
|
return 0;
|
|
return 0;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
@@ -1164,7 +1174,8 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
|
|
|
static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
|
|
static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
|
|
|
{
|
|
{
|
|
|
if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
|
|
if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
|
|
|
|
|
+ "bad ack timeout %u\n", us);
|
|
|
ah->acktimeout = (u32) -1;
|
|
ah->acktimeout = (u32) -1;
|
|
|
return false;
|
|
return false;
|
|
|
} else {
|
|
} else {
|
|
@@ -1178,7 +1189,8 @@ static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
|
|
|
static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
|
|
static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
|
|
|
{
|
|
{
|
|
|
if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
|
|
if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
|
|
|
|
|
+ "bad cts timeout %u\n", us);
|
|
|
ah->ctstimeout = (u32) -1;
|
|
ah->ctstimeout = (u32) -1;
|
|
|
return false;
|
|
return false;
|
|
|
} else {
|
|
} else {
|
|
@@ -1192,8 +1204,8 @@ static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
|
|
|
static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
|
|
static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
|
|
|
{
|
|
{
|
|
|
if (tu > 0xFFFF) {
|
|
if (tu > 0xFFFF) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
|
|
|
|
|
- "bad global tx timeout %u\n", tu);
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
|
|
|
|
|
+ "bad global tx timeout %u\n", tu);
|
|
|
ah->globaltxtimeout = (u32) -1;
|
|
ah->globaltxtimeout = (u32) -1;
|
|
|
return false;
|
|
return false;
|
|
|
} else {
|
|
} else {
|
|
@@ -1205,8 +1217,8 @@ static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
|
|
|
|
|
|
|
|
static void ath9k_hw_init_user_settings(struct ath_hw *ah)
|
|
static void ath9k_hw_init_user_settings(struct ath_hw *ah)
|
|
|
{
|
|
{
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
|
|
|
|
|
- ah->misc_mode);
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
|
|
|
|
|
+ ah->misc_mode);
|
|
|
|
|
|
|
|
if (ah->misc_mode != 0)
|
|
if (ah->misc_mode != 0)
|
|
|
REG_WRITE(ah, AR_PCU_MISC,
|
|
REG_WRITE(ah, AR_PCU_MISC,
|
|
@@ -1229,14 +1241,22 @@ const char *ath9k_hw_probe(u16 vendorid, u16 devid)
|
|
|
|
|
|
|
|
void ath9k_hw_detach(struct ath_hw *ah)
|
|
void ath9k_hw_detach(struct ath_hw *ah)
|
|
|
{
|
|
{
|
|
|
|
|
+ struct ath_common *common = ath9k_hw_common(ah);
|
|
|
|
|
+
|
|
|
|
|
+ if (common->state <= ATH_HW_INITIALIZED)
|
|
|
|
|
+ goto free_hw;
|
|
|
|
|
+
|
|
|
if (!AR_SREV_9100(ah))
|
|
if (!AR_SREV_9100(ah))
|
|
|
ath9k_hw_ani_disable(ah);
|
|
ath9k_hw_ani_disable(ah);
|
|
|
|
|
|
|
|
- ath9k_hw_rf_free(ah);
|
|
|
|
|
ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
|
|
ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
|
|
|
|
|
+
|
|
|
|
|
+free_hw:
|
|
|
|
|
+ ath9k_hw_rf_free(ah);
|
|
|
kfree(ah);
|
|
kfree(ah);
|
|
|
ah = NULL;
|
|
ah = NULL;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_detach);
|
|
|
|
|
|
|
|
/*******/
|
|
/*******/
|
|
|
/* INI */
|
|
/* INI */
|
|
@@ -1298,28 +1318,29 @@ static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
|
|
|
u32 reg, u32 value)
|
|
u32 reg, u32 value)
|
|
|
{
|
|
{
|
|
|
struct base_eep_header *pBase = &(pEepData->baseEepHeader);
|
|
struct base_eep_header *pBase = &(pEepData->baseEepHeader);
|
|
|
|
|
+ struct ath_common *common = ath9k_hw_common(ah);
|
|
|
|
|
|
|
|
switch (ah->hw_version.devid) {
|
|
switch (ah->hw_version.devid) {
|
|
|
case AR9280_DEVID_PCI:
|
|
case AR9280_DEVID_PCI:
|
|
|
if (reg == 0x7894) {
|
|
if (reg == 0x7894) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_EEPROM,
|
|
|
"ini VAL: %x EEPROM: %x\n", value,
|
|
"ini VAL: %x EEPROM: %x\n", value,
|
|
|
(pBase->version & 0xff));
|
|
(pBase->version & 0xff));
|
|
|
|
|
|
|
|
if ((pBase->version & 0xff) > 0x0a) {
|
|
if ((pBase->version & 0xff) > 0x0a) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
|
|
|
|
|
- "PWDCLKIND: %d\n",
|
|
|
|
|
- pBase->pwdclkind);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_EEPROM,
|
|
|
|
|
+ "PWDCLKIND: %d\n",
|
|
|
|
|
+ pBase->pwdclkind);
|
|
|
value &= ~AR_AN_TOP2_PWDCLKIND;
|
|
value &= ~AR_AN_TOP2_PWDCLKIND;
|
|
|
value |= AR_AN_TOP2_PWDCLKIND &
|
|
value |= AR_AN_TOP2_PWDCLKIND &
|
|
|
(pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
|
|
(pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
|
|
|
} else {
|
|
} else {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
|
|
|
|
|
- "PWDCLKIND Earlier Rev\n");
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_EEPROM,
|
|
|
|
|
+ "PWDCLKIND Earlier Rev\n");
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
|
|
|
|
|
- "final ini VAL: %x\n", value);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_EEPROM,
|
|
|
|
|
+ "final ini VAL: %x\n", value);
|
|
|
}
|
|
}
|
|
|
break;
|
|
break;
|
|
|
}
|
|
}
|
|
@@ -1374,8 +1395,7 @@ static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
static int ath9k_hw_process_ini(struct ath_hw *ah,
|
|
static int ath9k_hw_process_ini(struct ath_hw *ah,
|
|
|
- struct ath9k_channel *chan,
|
|
|
|
|
- enum ath9k_ht_macmode macmode)
|
|
|
|
|
|
|
+ struct ath9k_channel *chan)
|
|
|
{
|
|
{
|
|
|
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
|
|
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
|
|
|
int i, regWrites = 0;
|
|
int i, regWrites = 0;
|
|
@@ -1477,7 +1497,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
ath9k_hw_override_ini(ah, chan);
|
|
ath9k_hw_override_ini(ah, chan);
|
|
|
- ath9k_hw_set_regs(ah, chan, macmode);
|
|
|
|
|
|
|
+ ath9k_hw_set_regs(ah, chan);
|
|
|
ath9k_hw_init_chain_masks(ah);
|
|
ath9k_hw_init_chain_masks(ah);
|
|
|
|
|
|
|
|
if (OLC_FOR_AR9280_20_LATER)
|
|
if (OLC_FOR_AR9280_20_LATER)
|
|
@@ -1491,8 +1511,8 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
|
|
|
(u32) regulatory->power_limit));
|
|
(u32) regulatory->power_limit));
|
|
|
|
|
|
|
|
if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
|
|
if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
|
|
|
|
- "ar5416SetRfRegs failed\n");
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
|
|
|
|
|
+ "ar5416SetRfRegs failed\n");
|
|
|
return -EIO;
|
|
return -EIO;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
@@ -1697,16 +1717,14 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
|
|
|
|
|
|
|
|
REG_WRITE(ah, AR_RTC_RC, 0);
|
|
REG_WRITE(ah, AR_RTC_RC, 0);
|
|
|
if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
|
|
if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_RESET,
|
|
|
|
|
- "RTC stuck in MAC reset\n");
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
|
|
|
|
|
+ "RTC stuck in MAC reset\n");
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
if (!AR_SREV_9100(ah))
|
|
if (!AR_SREV_9100(ah))
|
|
|
REG_WRITE(ah, AR_RC, 0);
|
|
REG_WRITE(ah, AR_RC, 0);
|
|
|
|
|
|
|
|
- ath9k_hw_init_pll(ah, NULL);
|
|
|
|
|
-
|
|
|
|
|
if (AR_SREV_9100(ah))
|
|
if (AR_SREV_9100(ah))
|
|
|
udelay(50);
|
|
udelay(50);
|
|
|
|
|
|
|
@@ -1734,7 +1752,8 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
|
|
|
AR_RTC_STATUS_M,
|
|
AR_RTC_STATUS_M,
|
|
|
AR_RTC_STATUS_ON,
|
|
AR_RTC_STATUS_ON,
|
|
|
AH_WAIT_TIMEOUT)) {
|
|
AH_WAIT_TIMEOUT)) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
|
|
|
|
|
+ "RTC not waking up\n");
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
@@ -1759,8 +1778,7 @@ static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
-static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
|
|
|
|
|
- enum ath9k_ht_macmode macmode)
|
|
|
|
|
|
|
+static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
|
|
|
{
|
|
{
|
|
|
u32 phymode;
|
|
u32 phymode;
|
|
|
u32 enableDacFifo = 0;
|
|
u32 enableDacFifo = 0;
|
|
@@ -1779,12 +1797,10 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
|
|
|
(chan->chanmode == CHANNEL_G_HT40PLUS))
|
|
(chan->chanmode == CHANNEL_G_HT40PLUS))
|
|
|
phymode |= AR_PHY_FC_DYN2040_PRI_CH;
|
|
phymode |= AR_PHY_FC_DYN2040_PRI_CH;
|
|
|
|
|
|
|
|
- if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
|
|
|
|
|
- phymode |= AR_PHY_FC_DYN2040_EXT_CH;
|
|
|
|
|
}
|
|
}
|
|
|
REG_WRITE(ah, AR_PHY_TURBO, phymode);
|
|
REG_WRITE(ah, AR_PHY_TURBO, phymode);
|
|
|
|
|
|
|
|
- ath9k_hw_set11nmac2040(ah, macmode);
|
|
|
|
|
|
|
+ ath9k_hw_set11nmac2040(ah);
|
|
|
|
|
|
|
|
REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
|
|
REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
|
|
|
REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
|
|
REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
|
|
@@ -1810,17 +1826,18 @@ static bool ath9k_hw_chip_reset(struct ath_hw *ah,
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
static bool ath9k_hw_channel_change(struct ath_hw *ah,
|
|
static bool ath9k_hw_channel_change(struct ath_hw *ah,
|
|
|
- struct ath9k_channel *chan,
|
|
|
|
|
- enum ath9k_ht_macmode macmode)
|
|
|
|
|
|
|
+ struct ath9k_channel *chan)
|
|
|
{
|
|
{
|
|
|
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
|
|
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
|
|
|
|
|
+ struct ath_common *common = ath9k_hw_common(ah);
|
|
|
struct ieee80211_channel *channel = chan->chan;
|
|
struct ieee80211_channel *channel = chan->chan;
|
|
|
u32 synthDelay, qnum;
|
|
u32 synthDelay, qnum;
|
|
|
|
|
|
|
|
for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
|
|
for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
|
|
|
if (ath9k_hw_numtxpending(ah, qnum)) {
|
|
if (ath9k_hw_numtxpending(ah, qnum)) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
|
|
|
|
|
- "Transmit frames pending on queue %d\n", qnum);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_QUEUE,
|
|
|
|
|
+ "Transmit frames pending on "
|
|
|
|
|
+ "queue %d\n", qnum);
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
@@ -1828,19 +1845,19 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
|
|
|
REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
|
|
REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
|
|
|
if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
|
|
if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
|
|
|
AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
|
|
AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
|
|
|
|
- "Could not kill baseband RX\n");
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_FATAL,
|
|
|
|
|
+ "Could not kill baseband RX\n");
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
- ath9k_hw_set_regs(ah, chan, macmode);
|
|
|
|
|
|
|
+ ath9k_hw_set_regs(ah, chan);
|
|
|
|
|
|
|
|
if (AR_SREV_9280_10_OR_LATER(ah)) {
|
|
if (AR_SREV_9280_10_OR_LATER(ah)) {
|
|
|
ath9k_hw_ar9280_set_channel(ah, chan);
|
|
ath9k_hw_ar9280_set_channel(ah, chan);
|
|
|
} else {
|
|
} else {
|
|
|
if (!(ath9k_hw_set_channel(ah, chan))) {
|
|
if (!(ath9k_hw_set_channel(ah, chan))) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
|
|
|
|
- "Failed to set channel\n");
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_FATAL,
|
|
|
|
|
+ "Failed to set channel\n");
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
@@ -2342,17 +2359,16 @@ static void ath9k_enable_rfkill(struct ath_hw *ah)
|
|
|
int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
|
|
int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
|
|
|
bool bChannelChange)
|
|
bool bChannelChange)
|
|
|
{
|
|
{
|
|
|
|
|
+ struct ath_common *common = ath9k_hw_common(ah);
|
|
|
u32 saveLedState;
|
|
u32 saveLedState;
|
|
|
- struct ath_softc *sc = ah->ah_sc;
|
|
|
|
|
struct ath9k_channel *curchan = ah->curchan;
|
|
struct ath9k_channel *curchan = ah->curchan;
|
|
|
u32 saveDefAntenna;
|
|
u32 saveDefAntenna;
|
|
|
u32 macStaId1;
|
|
u32 macStaId1;
|
|
|
u64 tsf = 0;
|
|
u64 tsf = 0;
|
|
|
int i, rx_chainmask, r;
|
|
int i, rx_chainmask, r;
|
|
|
|
|
|
|
|
- ah->extprotspacing = sc->ht_extprotspacing;
|
|
|
|
|
- ah->txchainmask = sc->tx_chainmask;
|
|
|
|
|
- ah->rxchainmask = sc->rx_chainmask;
|
|
|
|
|
|
|
+ ah->txchainmask = common->tx_chainmask;
|
|
|
|
|
+ ah->rxchainmask = common->rx_chainmask;
|
|
|
|
|
|
|
|
if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
|
|
if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
|
|
|
return -EIO;
|
|
return -EIO;
|
|
@@ -2369,7 +2385,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
|
|
|
!(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
|
|
!(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
|
|
|
IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
|
|
IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
|
|
|
|
|
|
|
|
- if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
|
|
|
|
|
|
|
+ if (ath9k_hw_channel_change(ah, chan)) {
|
|
|
ath9k_hw_loadnf(ah, ah->curchan);
|
|
ath9k_hw_loadnf(ah, ah->curchan);
|
|
|
ath9k_hw_start_nfcal(ah);
|
|
ath9k_hw_start_nfcal(ah);
|
|
|
return 0;
|
|
return 0;
|
|
@@ -2400,7 +2416,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
if (!ath9k_hw_chip_reset(ah, chan)) {
|
|
if (!ath9k_hw_chip_reset(ah, chan)) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
|
|
|
return -EINVAL;
|
|
return -EINVAL;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
@@ -2429,7 +2445,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
|
|
|
REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
|
|
REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
|
|
|
AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
|
|
AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
|
|
|
}
|
|
}
|
|
|
- r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
|
|
|
|
|
|
|
+ r = ath9k_hw_process_ini(ah, chan);
|
|
|
if (r)
|
|
if (r)
|
|
|
return r;
|
|
return r;
|
|
|
|
|
|
|
@@ -2462,8 +2478,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
|
|
|
|
|
|
|
|
ath9k_hw_decrease_chain_power(ah, chan);
|
|
ath9k_hw_decrease_chain_power(ah, chan);
|
|
|
|
|
|
|
|
- REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
|
|
|
|
|
- REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
|
|
|
|
|
|
|
+ REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
|
|
|
|
|
+ REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
|
|
|
| macStaId1
|
|
| macStaId1
|
|
|
| AR_STA_ID1_RTS_USE_DEF
|
|
| AR_STA_ID1_RTS_USE_DEF
|
|
|
| (ah->config.
|
|
| (ah->config.
|
|
@@ -2471,14 +2487,11 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
|
|
|
| ah->sta_id1_defaults);
|
|
| ah->sta_id1_defaults);
|
|
|
ath9k_hw_set_operating_mode(ah, ah->opmode);
|
|
ath9k_hw_set_operating_mode(ah, ah->opmode);
|
|
|
|
|
|
|
|
- REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
|
|
|
|
|
- REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
|
|
|
|
|
|
|
+ ath_hw_setbssidmask(common);
|
|
|
|
|
|
|
|
REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
|
|
REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
|
|
|
|
|
|
|
|
- REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
|
|
|
|
|
- REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
|
|
|
|
|
- ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
|
|
|
|
|
|
|
+ ath9k_hw_write_associd(ah);
|
|
|
|
|
|
|
|
REG_WRITE(ah, AR_ISR, ~0);
|
|
REG_WRITE(ah, AR_ISR, ~0);
|
|
|
|
|
|
|
@@ -2558,13 +2571,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
|
|
|
u32 mask;
|
|
u32 mask;
|
|
|
mask = REG_READ(ah, AR_CFG);
|
|
mask = REG_READ(ah, AR_CFG);
|
|
|
if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
|
|
if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_RESET,
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_RESET,
|
|
|
"CFG Byte Swap Set 0x%x\n", mask);
|
|
"CFG Byte Swap Set 0x%x\n", mask);
|
|
|
} else {
|
|
} else {
|
|
|
mask =
|
|
mask =
|
|
|
INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
|
|
INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
|
|
|
REG_WRITE(ah, AR_CFG, mask);
|
|
REG_WRITE(ah, AR_CFG, mask);
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_RESET,
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_RESET,
|
|
|
"Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
|
|
"Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
|
|
|
}
|
|
}
|
|
|
} else {
|
|
} else {
|
|
@@ -2577,11 +2590,12 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
|
|
|
#endif
|
|
#endif
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
- if (ah->ah_sc->sc_flags & SC_OP_BTCOEX_ENABLED)
|
|
|
|
|
|
|
+ if (ah->btcoex_hw.enabled)
|
|
|
ath9k_hw_btcoex_enable(ah);
|
|
ath9k_hw_btcoex_enable(ah);
|
|
|
|
|
|
|
|
return 0;
|
|
return 0;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_reset);
|
|
|
|
|
|
|
|
/************************/
|
|
/************************/
|
|
|
/* Key Cache Management */
|
|
/* Key Cache Management */
|
|
@@ -2592,8 +2606,8 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
|
|
|
u32 keyType;
|
|
u32 keyType;
|
|
|
|
|
|
|
|
if (entry >= ah->caps.keycache_size) {
|
|
if (entry >= ah->caps.keycache_size) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
|
|
|
|
- "keychache entry %u out of range\n", entry);
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
|
|
|
|
|
+ "keychache entry %u out of range\n", entry);
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
@@ -2620,14 +2634,15 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
|
|
|
|
|
|
|
|
return true;
|
|
return true;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_keyreset);
|
|
|
|
|
|
|
|
bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
|
|
bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
|
|
|
{
|
|
{
|
|
|
u32 macHi, macLo;
|
|
u32 macHi, macLo;
|
|
|
|
|
|
|
|
if (entry >= ah->caps.keycache_size) {
|
|
if (entry >= ah->caps.keycache_size) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
|
|
|
|
- "keychache entry %u out of range\n", entry);
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
|
|
|
|
|
+ "keychache entry %u out of range\n", entry);
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
@@ -2648,18 +2663,20 @@ bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
|
|
|
|
|
|
|
|
return true;
|
|
return true;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_keysetmac);
|
|
|
|
|
|
|
|
bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
|
|
bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
|
|
|
const struct ath9k_keyval *k,
|
|
const struct ath9k_keyval *k,
|
|
|
const u8 *mac)
|
|
const u8 *mac)
|
|
|
{
|
|
{
|
|
|
const struct ath9k_hw_capabilities *pCap = &ah->caps;
|
|
const struct ath9k_hw_capabilities *pCap = &ah->caps;
|
|
|
|
|
+ struct ath_common *common = ath9k_hw_common(ah);
|
|
|
u32 key0, key1, key2, key3, key4;
|
|
u32 key0, key1, key2, key3, key4;
|
|
|
u32 keyType;
|
|
u32 keyType;
|
|
|
|
|
|
|
|
if (entry >= pCap->keycache_size) {
|
|
if (entry >= pCap->keycache_size) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
|
|
|
|
- "keycache entry %u out of range\n", entry);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_FATAL,
|
|
|
|
|
+ "keycache entry %u out of range\n", entry);
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
@@ -2669,9 +2686,9 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
|
|
|
break;
|
|
break;
|
|
|
case ATH9K_CIPHER_AES_CCM:
|
|
case ATH9K_CIPHER_AES_CCM:
|
|
|
if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
|
|
if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_ANY,
|
|
|
|
|
- "AES-CCM not supported by mac rev 0x%x\n",
|
|
|
|
|
- ah->hw_version.macRev);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_ANY,
|
|
|
|
|
+ "AES-CCM not supported by mac rev 0x%x\n",
|
|
|
|
|
+ ah->hw_version.macRev);
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
keyType = AR_KEYTABLE_TYPE_CCM;
|
|
keyType = AR_KEYTABLE_TYPE_CCM;
|
|
@@ -2680,15 +2697,15 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
|
|
|
keyType = AR_KEYTABLE_TYPE_TKIP;
|
|
keyType = AR_KEYTABLE_TYPE_TKIP;
|
|
|
if (ATH9K_IS_MIC_ENABLED(ah)
|
|
if (ATH9K_IS_MIC_ENABLED(ah)
|
|
|
&& entry + 64 >= pCap->keycache_size) {
|
|
&& entry + 64 >= pCap->keycache_size) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_ANY,
|
|
|
|
|
- "entry %u inappropriate for TKIP\n", entry);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_ANY,
|
|
|
|
|
+ "entry %u inappropriate for TKIP\n", entry);
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
break;
|
|
break;
|
|
|
case ATH9K_CIPHER_WEP:
|
|
case ATH9K_CIPHER_WEP:
|
|
|
if (k->kv_len < WLAN_KEY_LEN_WEP40) {
|
|
if (k->kv_len < WLAN_KEY_LEN_WEP40) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_ANY,
|
|
|
|
|
- "WEP key length %u too small\n", k->kv_len);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_ANY,
|
|
|
|
|
+ "WEP key length %u too small\n", k->kv_len);
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
if (k->kv_len <= WLAN_KEY_LEN_WEP40)
|
|
if (k->kv_len <= WLAN_KEY_LEN_WEP40)
|
|
@@ -2702,8 +2719,8 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
|
|
|
keyType = AR_KEYTABLE_TYPE_CLR;
|
|
keyType = AR_KEYTABLE_TYPE_CLR;
|
|
|
break;
|
|
break;
|
|
|
default:
|
|
default:
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
|
|
|
|
- "cipher %u not supported\n", k->kv_type);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_FATAL,
|
|
|
|
|
+ "cipher %u not supported\n", k->kv_type);
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
@@ -2845,6 +2862,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
|
|
|
|
|
|
|
|
return true;
|
|
return true;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
|
|
|
|
|
|
|
|
bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
|
|
bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
|
|
|
{
|
|
{
|
|
@@ -2855,6 +2873,7 @@ bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
|
|
|
}
|
|
}
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_keyisvalid);
|
|
|
|
|
|
|
|
/******************************/
|
|
/******************************/
|
|
|
/* Power Management (Chipset) */
|
|
/* Power Management (Chipset) */
|
|
@@ -2869,8 +2888,9 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
|
|
|
if (!AR_SREV_9100(ah))
|
|
if (!AR_SREV_9100(ah))
|
|
|
REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
|
|
REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
|
|
|
|
|
|
|
|
- REG_CLR_BIT(ah, (AR_RTC_RESET),
|
|
|
|
|
- AR_RTC_RESET_EN);
|
|
|
|
|
|
|
+ if(!AR_SREV_5416(ah))
|
|
|
|
|
+ REG_CLR_BIT(ah, (AR_RTC_RESET),
|
|
|
|
|
+ AR_RTC_RESET_EN);
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
|
|
|
|
|
@@ -2902,6 +2922,7 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
|
|
|
ATH9K_RESET_POWER_ON) != true) {
|
|
ATH9K_RESET_POWER_ON) != true) {
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
|
|
+ ath9k_hw_init_pll(ah, NULL);
|
|
|
}
|
|
}
|
|
|
if (AR_SREV_9100(ah))
|
|
if (AR_SREV_9100(ah))
|
|
|
REG_SET_BIT(ah, AR_RTC_RESET,
|
|
REG_SET_BIT(ah, AR_RTC_RESET,
|
|
@@ -2920,8 +2941,9 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
|
|
|
AR_RTC_FORCE_WAKE_EN);
|
|
AR_RTC_FORCE_WAKE_EN);
|
|
|
}
|
|
}
|
|
|
if (i == 0) {
|
|
if (i == 0) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
|
|
|
|
- "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
|
|
|
|
|
+ "Failed to wakeup in %uus\n",
|
|
|
|
|
+ POWER_UP_TIME / 20);
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
@@ -2931,9 +2953,9 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
|
|
|
return true;
|
|
return true;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
-static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
|
|
|
|
|
- enum ath9k_power_mode mode)
|
|
|
|
|
|
|
+bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
|
|
|
{
|
|
{
|
|
|
|
|
+ struct ath_common *common = ath9k_hw_common(ah);
|
|
|
int status = true, setChip = true;
|
|
int status = true, setChip = true;
|
|
|
static const char *modes[] = {
|
|
static const char *modes[] = {
|
|
|
"AWAKE",
|
|
"AWAKE",
|
|
@@ -2945,8 +2967,8 @@ static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
|
|
|
if (ah->power_mode == mode)
|
|
if (ah->power_mode == mode)
|
|
|
return status;
|
|
return status;
|
|
|
|
|
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
|
|
|
|
|
- modes[ah->power_mode], modes[mode]);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
|
|
|
|
|
+ modes[ah->power_mode], modes[mode]);
|
|
|
|
|
|
|
|
switch (mode) {
|
|
switch (mode) {
|
|
|
case ATH9K_PM_AWAKE:
|
|
case ATH9K_PM_AWAKE:
|
|
@@ -2960,59 +2982,15 @@ static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
|
|
|
ath9k_set_power_network_sleep(ah, setChip);
|
|
ath9k_set_power_network_sleep(ah, setChip);
|
|
|
break;
|
|
break;
|
|
|
default:
|
|
default:
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
|
|
|
|
|
- "Unknown power mode %u\n", mode);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_FATAL,
|
|
|
|
|
+ "Unknown power mode %u\n", mode);
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
ah->power_mode = mode;
|
|
ah->power_mode = mode;
|
|
|
|
|
|
|
|
return status;
|
|
return status;
|
|
|
}
|
|
}
|
|
|
-
|
|
|
|
|
-bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
|
|
|
|
|
-{
|
|
|
|
|
- unsigned long flags;
|
|
|
|
|
- bool ret;
|
|
|
|
|
-
|
|
|
|
|
- spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
|
|
|
|
|
- ret = ath9k_hw_setpower_nolock(ah, mode);
|
|
|
|
|
- spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
|
|
|
|
|
-
|
|
|
|
|
- return ret;
|
|
|
|
|
-}
|
|
|
|
|
-
|
|
|
|
|
-void ath9k_ps_wakeup(struct ath_softc *sc)
|
|
|
|
|
-{
|
|
|
|
|
- unsigned long flags;
|
|
|
|
|
-
|
|
|
|
|
- spin_lock_irqsave(&sc->sc_pm_lock, flags);
|
|
|
|
|
- if (++sc->ps_usecount != 1)
|
|
|
|
|
- goto unlock;
|
|
|
|
|
-
|
|
|
|
|
- ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
|
|
|
|
|
-
|
|
|
|
|
- unlock:
|
|
|
|
|
- spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
|
|
|
|
|
-}
|
|
|
|
|
-
|
|
|
|
|
-void ath9k_ps_restore(struct ath_softc *sc)
|
|
|
|
|
-{
|
|
|
|
|
- unsigned long flags;
|
|
|
|
|
-
|
|
|
|
|
- spin_lock_irqsave(&sc->sc_pm_lock, flags);
|
|
|
|
|
- if (--sc->ps_usecount != 0)
|
|
|
|
|
- goto unlock;
|
|
|
|
|
-
|
|
|
|
|
- if (sc->ps_enabled &&
|
|
|
|
|
- !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
|
|
|
|
|
- SC_OP_WAIT_FOR_CAB |
|
|
|
|
|
- SC_OP_WAIT_FOR_PSPOLL_DATA |
|
|
|
|
|
- SC_OP_WAIT_FOR_TX_ACK)))
|
|
|
|
|
- ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
|
|
|
|
|
-
|
|
|
|
|
- unlock:
|
|
|
|
|
- spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
|
|
|
|
|
-}
|
|
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_setpower);
|
|
|
|
|
|
|
|
/*
|
|
/*
|
|
|
* Helper for ASPM support.
|
|
* Helper for ASPM support.
|
|
@@ -3145,6 +3123,7 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
|
|
|
|
|
|
|
|
/**********************/
|
|
/**********************/
|
|
|
/* Interrupt Handling */
|
|
/* Interrupt Handling */
|
|
@@ -3168,6 +3147,7 @@ bool ath9k_hw_intrpend(struct ath_hw *ah)
|
|
|
|
|
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_intrpend);
|
|
|
|
|
|
|
|
bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
|
|
bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
|
|
|
{
|
|
{
|
|
@@ -3176,6 +3156,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
|
|
|
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
|
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
|
|
u32 sync_cause = 0;
|
|
u32 sync_cause = 0;
|
|
|
bool fatal_int = false;
|
|
bool fatal_int = false;
|
|
|
|
|
+ struct ath_common *common = ath9k_hw_common(ah);
|
|
|
|
|
|
|
|
if (!AR_SREV_9100(ah)) {
|
|
if (!AR_SREV_9100(ah)) {
|
|
|
if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
|
|
if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
|
|
@@ -3249,8 +3230,8 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
if (isr & AR_ISR_RXORN) {
|
|
if (isr & AR_ISR_RXORN) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
|
|
|
|
|
- "receive FIFO overrun interrupt\n");
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_INTERRUPT,
|
|
|
|
|
+ "receive FIFO overrun interrupt\n");
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
if (!AR_SREV_9100(ah)) {
|
|
if (!AR_SREV_9100(ah)) {
|
|
@@ -3292,25 +3273,25 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
|
|
|
|
|
|
|
|
if (fatal_int) {
|
|
if (fatal_int) {
|
|
|
if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
|
|
if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_ANY,
|
|
|
|
|
- "received PCI FATAL interrupt\n");
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_ANY,
|
|
|
|
|
+ "received PCI FATAL interrupt\n");
|
|
|
}
|
|
}
|
|
|
if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
|
|
if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_ANY,
|
|
|
|
|
- "received PCI PERR interrupt\n");
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_ANY,
|
|
|
|
|
+ "received PCI PERR interrupt\n");
|
|
|
}
|
|
}
|
|
|
*masked |= ATH9K_INT_FATAL;
|
|
*masked |= ATH9K_INT_FATAL;
|
|
|
}
|
|
}
|
|
|
if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
|
|
if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
|
|
|
|
|
- "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_INTERRUPT,
|
|
|
|
|
+ "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
|
|
|
REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
|
|
REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
|
|
|
REG_WRITE(ah, AR_RC, 0);
|
|
REG_WRITE(ah, AR_RC, 0);
|
|
|
*masked |= ATH9K_INT_FATAL;
|
|
*masked |= ATH9K_INT_FATAL;
|
|
|
}
|
|
}
|
|
|
if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
|
|
if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
|
|
|
|
|
- "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_INTERRUPT,
|
|
|
|
|
+ "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
|
|
REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
|
|
@@ -3319,17 +3300,19 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
|
|
|
|
|
|
|
|
return true;
|
|
return true;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_getisr);
|
|
|
|
|
|
|
|
enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
|
|
enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
|
|
|
{
|
|
{
|
|
|
u32 omask = ah->mask_reg;
|
|
u32 omask = ah->mask_reg;
|
|
|
u32 mask, mask2;
|
|
u32 mask, mask2;
|
|
|
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
|
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
|
|
|
|
+ struct ath_common *common = ath9k_hw_common(ah);
|
|
|
|
|
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
|
|
|
|
|
|
|
|
if (omask & ATH9K_INT_GLOBAL) {
|
|
if (omask & ATH9K_INT_GLOBAL) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
|
|
|
REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
|
|
REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
|
|
|
(void) REG_READ(ah, AR_IER);
|
|
(void) REG_READ(ah, AR_IER);
|
|
|
if (!AR_SREV_9100(ah)) {
|
|
if (!AR_SREV_9100(ah)) {
|
|
@@ -3386,7 +3369,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
|
|
|
mask2 |= AR_IMR_S2_CST;
|
|
mask2 |= AR_IMR_S2_CST;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
|
|
|
REG_WRITE(ah, AR_IMR, mask);
|
|
REG_WRITE(ah, AR_IMR, mask);
|
|
|
mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
|
|
mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
|
|
|
AR_IMR_S2_DTIM |
|
|
AR_IMR_S2_DTIM |
|
|
@@ -3406,7 +3389,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
if (ints & ATH9K_INT_GLOBAL) {
|
|
if (ints & ATH9K_INT_GLOBAL) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
|
|
|
REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
|
|
REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
|
|
|
if (!AR_SREV_9100(ah)) {
|
|
if (!AR_SREV_9100(ah)) {
|
|
|
REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
|
|
REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
|
|
@@ -3419,12 +3402,13 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
|
|
|
REG_WRITE(ah, AR_INTR_SYNC_MASK,
|
|
REG_WRITE(ah, AR_INTR_SYNC_MASK,
|
|
|
AR_INTR_SYNC_DEFAULT);
|
|
AR_INTR_SYNC_DEFAULT);
|
|
|
}
|
|
}
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
|
|
|
|
|
- REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
|
|
|
|
|
+ REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
return omask;
|
|
return omask;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_set_interrupts);
|
|
|
|
|
|
|
|
/*******************/
|
|
/*******************/
|
|
|
/* Beacon Handling */
|
|
/* Beacon Handling */
|
|
@@ -3467,9 +3451,9 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
|
|
|
AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
|
|
AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
|
|
|
break;
|
|
break;
|
|
|
default:
|
|
default:
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
|
|
|
|
|
- "%s: unsupported opmode: %d\n",
|
|
|
|
|
- __func__, ah->opmode);
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
|
|
|
|
|
+ "%s: unsupported opmode: %d\n",
|
|
|
|
|
+ __func__, ah->opmode);
|
|
|
return;
|
|
return;
|
|
|
break;
|
|
break;
|
|
|
}
|
|
}
|
|
@@ -3481,18 +3465,19 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
|
|
|
|
|
|
|
|
beacon_period &= ~ATH9K_BEACON_ENA;
|
|
beacon_period &= ~ATH9K_BEACON_ENA;
|
|
|
if (beacon_period & ATH9K_BEACON_RESET_TSF) {
|
|
if (beacon_period & ATH9K_BEACON_RESET_TSF) {
|
|
|
- beacon_period &= ~ATH9K_BEACON_RESET_TSF;
|
|
|
|
|
ath9k_hw_reset_tsf(ah);
|
|
ath9k_hw_reset_tsf(ah);
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
REG_SET_BIT(ah, AR_TIMER_MODE, flags);
|
|
REG_SET_BIT(ah, AR_TIMER_MODE, flags);
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_beaconinit);
|
|
|
|
|
|
|
|
void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
|
|
void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
|
|
|
const struct ath9k_beacon_state *bs)
|
|
const struct ath9k_beacon_state *bs)
|
|
|
{
|
|
{
|
|
|
u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
|
|
u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
|
|
|
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
|
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
|
|
|
|
+ struct ath_common *common = ath9k_hw_common(ah);
|
|
|
|
|
|
|
|
REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
|
|
REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
|
|
|
|
|
|
|
@@ -3518,10 +3503,10 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
|
|
|
else
|
|
else
|
|
|
nextTbtt = bs->bs_nexttbtt;
|
|
nextTbtt = bs->bs_nexttbtt;
|
|
|
|
|
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
|
|
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
|
|
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
|
|
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
|
|
|
|
|
+ ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
|
|
|
|
|
+ ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
|
|
|
|
|
+ ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
|
|
|
|
|
|
|
|
REG_WRITE(ah, AR_NEXT_DTIM,
|
|
REG_WRITE(ah, AR_NEXT_DTIM,
|
|
|
TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
|
|
TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
|
|
@@ -3549,6 +3534,7 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
|
|
|
/* TSF Out of Range Threshold */
|
|
/* TSF Out of Range Threshold */
|
|
|
REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
|
|
REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
|
|
|
|
|
|
|
|
/*******************/
|
|
/*******************/
|
|
|
/* HW Capabilities */
|
|
/* HW Capabilities */
|
|
@@ -3558,7 +3544,8 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
|
|
|
{
|
|
{
|
|
|
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
|
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
|
|
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
|
|
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
|
|
|
- struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info;
|
|
|
|
|
|
|
+ struct ath_common *common = ath9k_hw_common(ah);
|
|
|
|
|
+ struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
|
|
|
|
|
|
|
|
u16 capField = 0, eeval;
|
|
u16 capField = 0, eeval;
|
|
|
|
|
|
|
@@ -3579,8 +3566,8 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
|
|
|
regulatory->current_rd += 5;
|
|
regulatory->current_rd += 5;
|
|
|
else if (regulatory->current_rd == 0x41)
|
|
else if (regulatory->current_rd == 0x41)
|
|
|
regulatory->current_rd = 0x43;
|
|
regulatory->current_rd = 0x43;
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
|
|
|
|
|
- "regdomain mapped to 0x%x\n", regulatory->current_rd);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_REGULATORY,
|
|
|
|
|
+ "regdomain mapped to 0x%x\n", regulatory->current_rd);
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
|
|
eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
|
|
@@ -3719,7 +3706,10 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
|
|
|
AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
|
|
AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
- pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
|
|
|
|
|
|
|
+ /* Advertise midband for AR5416 with FCC midband set in eeprom */
|
|
|
|
|
+ if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
|
|
|
|
|
+ AR_SREV_5416(ah))
|
|
|
|
|
+ pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
|
|
|
|
|
|
|
|
pCap->num_antcfg_5ghz =
|
|
pCap->num_antcfg_5ghz =
|
|
|
ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
|
|
ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
|
|
@@ -3727,18 +3717,18 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
|
|
|
ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
|
|
ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
|
|
|
|
|
|
|
|
if (AR_SREV_9280_10_OR_LATER(ah) &&
|
|
if (AR_SREV_9280_10_OR_LATER(ah) &&
|
|
|
- ath_btcoex_supported(ah->hw_version.subsysid)) {
|
|
|
|
|
- btcoex_info->btactive_gpio = ATH_BTACTIVE_GPIO;
|
|
|
|
|
- btcoex_info->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
|
|
|
|
|
|
|
+ ath9k_hw_btcoex_supported(ah)) {
|
|
|
|
|
+ btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
|
|
|
|
|
+ btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
|
|
|
|
|
|
|
|
if (AR_SREV_9285(ah)) {
|
|
if (AR_SREV_9285(ah)) {
|
|
|
- btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_3WIRE;
|
|
|
|
|
- btcoex_info->btpriority_gpio = ATH_BTPRIORITY_GPIO;
|
|
|
|
|
|
|
+ btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
|
|
|
|
|
+ btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
|
|
|
} else {
|
|
} else {
|
|
|
- btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_2WIRE;
|
|
|
|
|
|
|
+ btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
|
|
|
}
|
|
}
|
|
|
} else {
|
|
} else {
|
|
|
- btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_NONE;
|
|
|
|
|
|
|
+ btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
|
|
|
|
|
@@ -3812,6 +3802,7 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_getcapability);
|
|
|
|
|
|
|
|
bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
|
|
bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
|
|
|
u32 capability, u32 setting, int *status)
|
|
u32 capability, u32 setting, int *status)
|
|
@@ -3845,6 +3836,7 @@ bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
|
|
|
return false;
|
|
return false;
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_setcapability);
|
|
|
|
|
|
|
|
/****************************/
|
|
/****************************/
|
|
|
/* GPIO / RFKILL / Antennae */
|
|
/* GPIO / RFKILL / Antennae */
|
|
@@ -3882,7 +3874,7 @@ void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
|
|
|
{
|
|
{
|
|
|
u32 gpio_shift;
|
|
u32 gpio_shift;
|
|
|
|
|
|
|
|
- ASSERT(gpio < ah->caps.num_gpio_pins);
|
|
|
|
|
|
|
+ BUG_ON(gpio >= ah->caps.num_gpio_pins);
|
|
|
|
|
|
|
|
gpio_shift = gpio << 1;
|
|
gpio_shift = gpio << 1;
|
|
|
|
|
|
|
@@ -3891,6 +3883,7 @@ void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
|
|
|
(AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
|
|
(AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
|
|
|
(AR_GPIO_OE_OUT_DRV << gpio_shift));
|
|
(AR_GPIO_OE_OUT_DRV << gpio_shift));
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
|
|
|
|
|
|
|
|
u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
|
|
u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
|
|
|
{
|
|
{
|
|
@@ -3909,6 +3902,7 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
|
|
|
else
|
|
else
|
|
|
return MS_REG_READ(AR, gpio) != 0;
|
|
return MS_REG_READ(AR, gpio) != 0;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_gpio_get);
|
|
|
|
|
|
|
|
void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
|
|
void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
|
|
|
u32 ah_signal_type)
|
|
u32 ah_signal_type)
|
|
@@ -3924,22 +3918,26 @@ void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
|
|
|
(AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
|
|
(AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
|
|
|
(AR_GPIO_OE_OUT_DRV << gpio_shift));
|
|
(AR_GPIO_OE_OUT_DRV << gpio_shift));
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_cfg_output);
|
|
|
|
|
|
|
|
void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
|
|
void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
|
|
|
{
|
|
{
|
|
|
REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
|
|
REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
|
|
|
AR_GPIO_BIT(gpio));
|
|
AR_GPIO_BIT(gpio));
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_set_gpio);
|
|
|
|
|
|
|
|
u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
|
|
u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
|
|
|
{
|
|
{
|
|
|
return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
|
|
return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_getdefantenna);
|
|
|
|
|
|
|
|
void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
|
|
void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
|
|
|
{
|
|
{
|
|
|
REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
|
|
REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_setantenna);
|
|
|
|
|
|
|
|
bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
|
|
bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
|
|
|
enum ath9k_ant_setting settings,
|
|
enum ath9k_ant_setting settings,
|
|
@@ -4002,6 +4000,7 @@ u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
|
|
|
|
|
|
|
|
return bits;
|
|
return bits;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_getrxfilter);
|
|
|
|
|
|
|
|
void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
|
|
void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
|
|
|
{
|
|
{
|
|
@@ -4023,19 +4022,30 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
|
|
|
REG_WRITE(ah, AR_RXCFG,
|
|
REG_WRITE(ah, AR_RXCFG,
|
|
|
REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
|
|
REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_setrxfilter);
|
|
|
|
|
|
|
|
bool ath9k_hw_phy_disable(struct ath_hw *ah)
|
|
bool ath9k_hw_phy_disable(struct ath_hw *ah)
|
|
|
{
|
|
{
|
|
|
- return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
|
|
|
|
|
|
|
+ if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
|
|
|
|
|
+ return false;
|
|
|
|
|
+
|
|
|
|
|
+ ath9k_hw_init_pll(ah, NULL);
|
|
|
|
|
+ return true;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_phy_disable);
|
|
|
|
|
|
|
|
bool ath9k_hw_disable(struct ath_hw *ah)
|
|
bool ath9k_hw_disable(struct ath_hw *ah)
|
|
|
{
|
|
{
|
|
|
if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
|
|
if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
|
|
|
return false;
|
|
return false;
|
|
|
|
|
|
|
|
- return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
|
|
|
|
|
|
|
+ if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
|
|
|
|
|
+ return false;
|
|
|
|
|
+
|
|
|
|
|
+ ath9k_hw_init_pll(ah, NULL);
|
|
|
|
|
+ return true;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_disable);
|
|
|
|
|
|
|
|
void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
|
|
void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
|
|
|
{
|
|
{
|
|
@@ -4052,35 +4062,36 @@ void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
|
|
|
min((u32) MAX_RATE_POWER,
|
|
min((u32) MAX_RATE_POWER,
|
|
|
(u32) regulatory->power_limit));
|
|
(u32) regulatory->power_limit));
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
|
|
|
|
|
|
|
|
void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
|
|
void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
|
|
|
{
|
|
{
|
|
|
- memcpy(ah->macaddr, mac, ETH_ALEN);
|
|
|
|
|
|
|
+ memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_setmac);
|
|
|
|
|
|
|
|
void ath9k_hw_setopmode(struct ath_hw *ah)
|
|
void ath9k_hw_setopmode(struct ath_hw *ah)
|
|
|
{
|
|
{
|
|
|
ath9k_hw_set_operating_mode(ah, ah->opmode);
|
|
ath9k_hw_set_operating_mode(ah, ah->opmode);
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_setopmode);
|
|
|
|
|
|
|
|
void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
|
|
void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
|
|
|
{
|
|
{
|
|
|
REG_WRITE(ah, AR_MCAST_FIL0, filter0);
|
|
REG_WRITE(ah, AR_MCAST_FIL0, filter0);
|
|
|
REG_WRITE(ah, AR_MCAST_FIL1, filter1);
|
|
REG_WRITE(ah, AR_MCAST_FIL1, filter1);
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
|
|
|
|
|
|
|
|
-void ath9k_hw_setbssidmask(struct ath_softc *sc)
|
|
|
|
|
|
|
+void ath9k_hw_write_associd(struct ath_hw *ah)
|
|
|
{
|
|
{
|
|
|
- REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
|
|
|
|
|
- REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
|
|
|
|
|
-}
|
|
|
|
|
|
|
+ struct ath_common *common = ath9k_hw_common(ah);
|
|
|
|
|
|
|
|
-void ath9k_hw_write_associd(struct ath_softc *sc)
|
|
|
|
|
-{
|
|
|
|
|
- REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
|
|
|
|
|
- REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
|
|
|
|
|
- ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
|
|
|
|
|
|
|
+ REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
|
|
|
|
|
+ REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
|
|
|
|
|
+ ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_write_associd);
|
|
|
|
|
|
|
|
u64 ath9k_hw_gettsf64(struct ath_hw *ah)
|
|
u64 ath9k_hw_gettsf64(struct ath_hw *ah)
|
|
|
{
|
|
{
|
|
@@ -4091,24 +4102,25 @@ u64 ath9k_hw_gettsf64(struct ath_hw *ah)
|
|
|
|
|
|
|
|
return tsf;
|
|
return tsf;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_gettsf64);
|
|
|
|
|
|
|
|
void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
|
|
void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
|
|
|
{
|
|
{
|
|
|
REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
|
|
REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
|
|
|
REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
|
|
REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_settsf64);
|
|
|
|
|
|
|
|
void ath9k_hw_reset_tsf(struct ath_hw *ah)
|
|
void ath9k_hw_reset_tsf(struct ath_hw *ah)
|
|
|
{
|
|
{
|
|
|
- ath9k_ps_wakeup(ah->ah_sc);
|
|
|
|
|
if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
|
|
if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
|
|
|
AH_TSF_WRITE_TIMEOUT))
|
|
AH_TSF_WRITE_TIMEOUT))
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_RESET,
|
|
|
|
|
- "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
|
|
|
|
|
+ "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
|
|
|
|
|
|
|
|
REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
|
|
REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
|
|
|
- ath9k_ps_restore(ah->ah_sc);
|
|
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_reset_tsf);
|
|
|
|
|
|
|
|
void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
|
|
void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
|
|
|
{
|
|
{
|
|
@@ -4117,11 +4129,13 @@ void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
|
|
|
else
|
|
else
|
|
|
ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
|
|
ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
|
|
|
|
|
|
|
|
bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
|
|
bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
|
|
|
{
|
|
{
|
|
|
if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
|
|
if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
|
|
|
|
|
+ "bad slot time %u\n", us);
|
|
|
ah->slottime = (u32) -1;
|
|
ah->slottime = (u32) -1;
|
|
|
return false;
|
|
return false;
|
|
|
} else {
|
|
} else {
|
|
@@ -4130,13 +4144,14 @@ bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
|
|
|
return true;
|
|
return true;
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_setslottime);
|
|
|
|
|
|
|
|
-void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
|
|
|
|
|
|
|
+void ath9k_hw_set11nmac2040(struct ath_hw *ah)
|
|
|
{
|
|
{
|
|
|
|
|
+ struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
|
|
|
u32 macmode;
|
|
u32 macmode;
|
|
|
|
|
|
|
|
- if (mode == ATH9K_HT_MACMODE_2040 &&
|
|
|
|
|
- !ah->config.cwm_ignore_extcca)
|
|
|
|
|
|
|
+ if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
|
|
|
macmode = AR_2040_JOINED_RX_CLEAR;
|
|
macmode = AR_2040_JOINED_RX_CLEAR;
|
|
|
else
|
|
else
|
|
|
macmode = 0;
|
|
macmode = 0;
|
|
@@ -4193,6 +4208,7 @@ u32 ath9k_hw_gettsf32(struct ath_hw *ah)
|
|
|
{
|
|
{
|
|
|
return REG_READ(ah, AR_TSF_L32);
|
|
return REG_READ(ah, AR_TSF_L32);
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_gettsf32);
|
|
|
|
|
|
|
|
struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
|
|
struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
|
|
|
void (*trigger)(void *),
|
|
void (*trigger)(void *),
|
|
@@ -4206,8 +4222,9 @@ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
|
|
|
timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
|
|
timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
|
|
|
|
|
|
|
|
if (timer == NULL) {
|
|
if (timer == NULL) {
|
|
|
- printk(KERN_DEBUG "Failed to allocate memory"
|
|
|
|
|
- "for hw timer[%d]\n", timer_index);
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
|
|
|
|
|
+ "Failed to allocate memory"
|
|
|
|
|
+ "for hw timer[%d]\n", timer_index);
|
|
|
return NULL;
|
|
return NULL;
|
|
|
}
|
|
}
|
|
|
|
|
|
|
@@ -4220,10 +4237,12 @@ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
|
|
|
|
|
|
|
|
return timer;
|
|
return timer;
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath_gen_timer_alloc);
|
|
|
|
|
|
|
|
-void ath_gen_timer_start(struct ath_hw *ah,
|
|
|
|
|
- struct ath_gen_timer *timer,
|
|
|
|
|
- u32 timer_next, u32 timer_period)
|
|
|
|
|
|
|
+void ath9k_hw_gen_timer_start(struct ath_hw *ah,
|
|
|
|
|
+ struct ath_gen_timer *timer,
|
|
|
|
|
+ u32 timer_next,
|
|
|
|
|
+ u32 timer_period)
|
|
|
{
|
|
{
|
|
|
struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
|
|
struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
|
|
|
u32 tsf;
|
|
u32 tsf;
|
|
@@ -4234,8 +4253,9 @@ void ath_gen_timer_start(struct ath_hw *ah,
|
|
|
|
|
|
|
|
tsf = ath9k_hw_gettsf32(ah);
|
|
tsf = ath9k_hw_gettsf32(ah);
|
|
|
|
|
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER, "curent tsf %x period %x"
|
|
|
|
|
- "timer_next %x\n", tsf, timer_period, timer_next);
|
|
|
|
|
|
|
+ ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
|
|
|
|
|
+ "curent tsf %x period %x"
|
|
|
|
|
+ "timer_next %x\n", tsf, timer_period, timer_next);
|
|
|
|
|
|
|
|
/*
|
|
/*
|
|
|
* Pull timer_next forward if the current TSF already passed it
|
|
* Pull timer_next forward if the current TSF already passed it
|
|
@@ -4258,15 +4278,10 @@ void ath_gen_timer_start(struct ath_hw *ah,
|
|
|
REG_SET_BIT(ah, AR_IMR_S5,
|
|
REG_SET_BIT(ah, AR_IMR_S5,
|
|
|
(SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
|
|
(SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
|
|
|
SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
|
|
SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
|
|
|
-
|
|
|
|
|
- if ((ah->ah_sc->imask & ATH9K_INT_GENTIMER) == 0) {
|
|
|
|
|
- ath9k_hw_set_interrupts(ah, 0);
|
|
|
|
|
- ah->ah_sc->imask |= ATH9K_INT_GENTIMER;
|
|
|
|
|
- ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
|
|
|
|
|
- }
|
|
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
|
|
|
|
|
|
|
|
-void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
|
|
|
|
|
|
|
+void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
|
|
|
{
|
|
{
|
|
|
struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
|
|
struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
|
|
|
|
|
|
|
@@ -4285,14 +4300,8 @@ void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
|
|
|
SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
|
|
SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
|
|
|
|
|
|
|
|
clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
|
|
clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
|
|
|
-
|
|
|
|
|
- /* if no timer is enabled, turn off interrupt mask */
|
|
|
|
|
- if (timer_table->timer_mask.val == 0) {
|
|
|
|
|
- ath9k_hw_set_interrupts(ah, 0);
|
|
|
|
|
- ah->ah_sc->imask &= ~ATH9K_INT_GENTIMER;
|
|
|
|
|
- ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
|
|
|
|
|
- }
|
|
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
|
|
|
|
|
|
|
|
void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
|
|
void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
|
|
|
{
|
|
{
|
|
@@ -4302,6 +4311,7 @@ void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
|
|
|
timer_table->timers[timer->index] = NULL;
|
|
timer_table->timers[timer->index] = NULL;
|
|
|
kfree(timer);
|
|
kfree(timer);
|
|
|
}
|
|
}
|
|
|
|
|
+EXPORT_SYMBOL(ath_gen_timer_free);
|
|
|
|
|
|
|
|
/*
|
|
/*
|
|
|
* Generic Timer Interrupts handling
|
|
* Generic Timer Interrupts handling
|
|
@@ -4310,6 +4320,7 @@ void ath_gen_timer_isr(struct ath_hw *ah)
|
|
|
{
|
|
{
|
|
|
struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
|
|
struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
|
|
|
struct ath_gen_timer *timer;
|
|
struct ath_gen_timer *timer;
|
|
|
|
|
+ struct ath_common *common = ath9k_hw_common(ah);
|
|
|
u32 trigger_mask, thresh_mask, index;
|
|
u32 trigger_mask, thresh_mask, index;
|
|
|
|
|
|
|
|
/* get hardware generic timer interrupt status */
|
|
/* get hardware generic timer interrupt status */
|
|
@@ -4324,8 +4335,8 @@ void ath_gen_timer_isr(struct ath_hw *ah)
|
|
|
index = rightmost_index(timer_table, &thresh_mask);
|
|
index = rightmost_index(timer_table, &thresh_mask);
|
|
|
timer = timer_table->timers[index];
|
|
timer = timer_table->timers[index];
|
|
|
BUG_ON(!timer);
|
|
BUG_ON(!timer);
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER,
|
|
|
|
|
- "TSF overflow for Gen timer %d\n", index);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_HWTIMER,
|
|
|
|
|
+ "TSF overflow for Gen timer %d\n", index);
|
|
|
timer->overflow(timer->arg);
|
|
timer->overflow(timer->arg);
|
|
|
}
|
|
}
|
|
|
|
|
|
|
@@ -4333,21 +4344,9 @@ void ath_gen_timer_isr(struct ath_hw *ah)
|
|
|
index = rightmost_index(timer_table, &trigger_mask);
|
|
index = rightmost_index(timer_table, &trigger_mask);
|
|
|
timer = timer_table->timers[index];
|
|
timer = timer_table->timers[index];
|
|
|
BUG_ON(!timer);
|
|
BUG_ON(!timer);
|
|
|
- DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER,
|
|
|
|
|
- "Gen timer[%d] trigger\n", index);
|
|
|
|
|
|
|
+ ath_print(common, ATH_DBG_HWTIMER,
|
|
|
|
|
+ "Gen timer[%d] trigger\n", index);
|
|
|
timer->trigger(timer->arg);
|
|
timer->trigger(timer->arg);
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
|
-
|
|
|
|
|
-/*
|
|
|
|
|
- * Primitive to disable ASPM
|
|
|
|
|
- */
|
|
|
|
|
-void ath_pcie_aspm_disable(struct ath_softc *sc)
|
|
|
|
|
-{
|
|
|
|
|
- struct pci_dev *pdev = to_pci_dev(sc->dev);
|
|
|
|
|
- u8 aspm;
|
|
|
|
|
-
|
|
|
|
|
- pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
|
|
|
|
|
- aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
|
|
|
|
|
- pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
|
|
|
|
|
-}
|
|
|
|
|
|
|
+EXPORT_SYMBOL(ath_gen_timer_isr);
|