|
@@ -165,6 +165,7 @@ struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay,
|
|
|
unsigned int vfieldrate, hperiod;
|
|
|
int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync;
|
|
|
int interlace;
|
|
|
+ u64 tmp;
|
|
|
|
|
|
/* allocate the drm_display_mode structure. If failure, we will
|
|
|
* return directly
|
|
@@ -322,8 +323,11 @@ struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay,
|
|
|
drm_mode->vsync_end = drm_mode->vsync_start + vsync;
|
|
|
}
|
|
|
/* 15/13. Find pixel clock frequency (kHz for xf86) */
|
|
|
- drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod;
|
|
|
- drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP;
|
|
|
+ tmp = drm_mode->htotal; /* perform intermediate calcs in u64 */
|
|
|
+ tmp *= HV_FACTOR * 1000;
|
|
|
+ do_div(tmp, hperiod);
|
|
|
+ tmp -= drm_mode->clock % CVT_CLOCK_STEP;
|
|
|
+ drm_mode->clock = tmp;
|
|
|
/* 18/16. Find actual vertical frame frequency */
|
|
|
/* ignore - just set the mode flag for interlaced */
|
|
|
if (interlaced) {
|