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@@ -205,6 +205,18 @@ static const struct aspeed_clk_soc_data ast2400_data = {
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.calc_pll = aspeed_ast2400_calc_pll,
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};
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+static int aspeed_clk_is_enabled(struct clk_hw *hw)
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+{
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+ struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
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+ u32 clk = BIT(gate->clock_idx);
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+ u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
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+ u32 reg;
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+
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+ regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®);
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+
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+ return ((reg & clk) == enval) ? 1 : 0;
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+}
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+
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static int aspeed_clk_enable(struct clk_hw *hw)
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{
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struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
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@@ -215,6 +227,11 @@ static int aspeed_clk_enable(struct clk_hw *hw)
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spin_lock_irqsave(gate->lock, flags);
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+ if (aspeed_clk_is_enabled(hw)) {
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+ spin_unlock_irqrestore(gate->lock, flags);
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+ return 0;
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+ }
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+
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if (gate->reset_idx >= 0) {
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/* Put IP in reset */
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regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst);
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@@ -255,18 +272,6 @@ static void aspeed_clk_disable(struct clk_hw *hw)
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spin_unlock_irqrestore(gate->lock, flags);
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}
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-static int aspeed_clk_is_enabled(struct clk_hw *hw)
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-{
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- struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
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- u32 clk = BIT(gate->clock_idx);
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- u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
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- u32 reg;
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-
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- regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®);
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-
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- return ((reg & clk) == enval) ? 1 : 0;
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-}
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-
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static const struct clk_ops aspeed_clk_gate_ops = {
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.enable = aspeed_clk_enable,
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.disable = aspeed_clk_disable,
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