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@@ -1211,15 +1211,12 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
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}
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}
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-static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
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+static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
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{
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u32 val;
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bool enabled;
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- if (HAS_PCH_LPT(dev_priv->dev)) {
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- DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
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- return;
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- }
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+ WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
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val = I915_READ(PCH_DREF_CONTROL);
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enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
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@@ -10077,7 +10074,7 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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/* PCH refclock must be enabled first */
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- assert_pch_refclk_enabled(dev_priv);
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+ ibx_assert_pch_refclk_enabled(dev_priv);
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I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
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@@ -10145,8 +10142,6 @@ static void intel_shared_dpll_init(struct drm_device *dev)
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dev_priv->num_shared_dpll = 0;
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BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
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- DRM_DEBUG_KMS("%i shared PLLs initialized\n",
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- dev_priv->num_shared_dpll);
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}
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static void intel_crtc_init(struct drm_device *dev, int pipe)
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