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@@ -519,15 +519,6 @@ static void denali_setup_dma32(struct denali_nand_info *denali,
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denali->host_write(denali, mode | 0x14000, 0x2400);
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}
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-static void denali_setup_dma(struct denali_nand_info *denali,
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- dma_addr_t dma_addr, int page, int write)
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-{
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- if (denali->caps & DENALI_CAP_DMA_64BIT)
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- denali_setup_dma64(denali, dma_addr, page, write);
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- else
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- denali_setup_dma32(denali, dma_addr, page, write);
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-}
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-
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static int denali_pio_read(struct denali_nand_info *denali, void *buf,
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size_t size, int page, int raw)
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{
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@@ -619,7 +610,7 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
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iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
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denali_reset_irq(denali);
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- denali_setup_dma(denali, dma_addr, page, write);
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+ denali->setup_dma(denali, dma_addr, page, write);
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irq_status = denali_wait_for_irq(denali, irq_mask);
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if (!(irq_status & INTR__DMA_CMD_COMP))
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@@ -1314,6 +1305,10 @@ int denali_init(struct denali_nand_info *denali)
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if (denali->dma_avail) {
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chip->options |= NAND_USE_BOUNCE_BUFFER;
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chip->buf_align = 16;
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+ if (denali->caps & DENALI_CAP_DMA_64BIT)
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+ denali->setup_dma = denali_setup_dma64;
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+ else
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+ denali->setup_dma = denali_setup_dma32;
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}
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chip->bbt_options |= NAND_BBT_USE_FLASH;
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