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@@ -37,6 +37,8 @@
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#define ST_LSM6DSX_REG_FIFO_THH_ADDR 0x07
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#define ST_LSM6DSX_FIFO_TH_MASK GENMASK(11, 0)
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#define ST_LSM6DSX_REG_FIFO_DEC_GXL_ADDR 0x08
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+#define ST_LSM6DSX_REG_HLACTIVE_ADDR 0x12
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+#define ST_LSM6DSX_REG_HLACTIVE_MASK BIT(5)
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#define ST_LSM6DSX_REG_FIFO_MODE_ADDR 0x0a
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#define ST_LSM6DSX_FIFO_MODE_MASK GENMASK(2, 0)
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#define ST_LSM6DSX_FIFO_ODR_MASK GENMASK(6, 3)
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@@ -417,6 +419,7 @@ int st_lsm6dsx_fifo_setup(struct st_lsm6dsx_hw *hw)
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{
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struct iio_buffer *buffer;
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unsigned long irq_type;
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+ bool irq_active_low;
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int i, err;
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irq_type = irqd_get_trigger_type(irq_get_irq_data(hw->irq));
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@@ -424,12 +427,23 @@ int st_lsm6dsx_fifo_setup(struct st_lsm6dsx_hw *hw)
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switch (irq_type) {
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case IRQF_TRIGGER_HIGH:
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case IRQF_TRIGGER_RISING:
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+ irq_active_low = false;
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+ break;
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+ case IRQF_TRIGGER_LOW:
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+ case IRQF_TRIGGER_FALLING:
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+ irq_active_low = true;
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break;
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default:
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dev_info(hw->dev, "mode %lx unsupported\n", irq_type);
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return -EINVAL;
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}
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+ err = st_lsm6dsx_write_with_mask(hw, ST_LSM6DSX_REG_HLACTIVE_ADDR,
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+ ST_LSM6DSX_REG_HLACTIVE_MASK,
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+ irq_active_low);
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+ if (err < 0)
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+ return err;
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+
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err = devm_request_threaded_irq(hw->dev, hw->irq,
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st_lsm6dsx_handler_irq,
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st_lsm6dsx_handler_thread,
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